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YORK UNIVERSITY CSE Mokhtar Aboelaze CSE Winter  YORK UNIVERSITY CSE Pipelining  Introduction YORK UNIVERSITY CSE Mokhtar Aboelaze CSE Winter  YORK UNIVERSITY CSE Pipelining  Introduction

YORK UNIVERSITY CSE Mokhtar Aboelaze CSE Winter YORK UNIVERSITY CSE Pipelining Introduction - PDF document

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YORK UNIVERSITY CSE Mokhtar Aboelaze CSE Winter YORK UNIVERSITY CSE Pipelining Introduction - PPT Presentation

That can lead to either increasing the clock speed or decreasing the power consumption Multiprocessing can be also used to increase speed or reduce power brPage 2br YORK UNIVERSITY CSE4210 Pipelining ab yn xn2 xn1 xn tion multiplica one and additi ID: 26469

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1 YORK UNIVERSITYCSE4210 Chapter 3Pipelining and parallel Processing Mokhtar Aboelaze CSE4210 Winter 2012 Pipelining --Introduction•Pipelining can be us•That can lead to either increasing the •Multiprocessing can be also used to 2 YORK UNIVERSITYCSE4210 D x(n-2)x(n-1)x(n) 2(1,2tionmultiplica one and additions twois herepath critical ThemuladdsmuladdsTTfTTT YORK UNIVERSITYCSE4210 x(n)x(n)y(n)y(n-1)b(n)b(n-1)b(2k)b(2k+1)a(2k+1)y(2k)y(2k+1)x(2k+1)x(2k)Pipelining 3 •Advantages–Could be used to reduce power and/or to •Disadvantages–Increases number of delay elements (latches –Increases latency YORK UNIVERSITYCSE4210 Cutset: a cutsetwhere the •We can place latches on a 4 YORK UNIVERSITYCSE4210 D x(n-2)x(n-1)x(n) D YORK UNIVERSITYCSE4210 DA1A2A4A6A3A5 DA1A2A4A6A3A5 DA1A2A4A6A3A5 Critical Path? 5 •Reversing the direction of all the edges in YORK UNIVERSITYCSE4210 ooooo bc ooooo bc 6 YORK UNIVERSITYCSE4210Fine-Grain Pipelining D D x(n) Multiplication time = 10Addition time = 2 YORK UNIVERSITYCSE4210Fine grain Pipelining 7 YORK UNIVERSITYCSE4210Parallel Processing)3()13()23()23()13()3()13()13()23()13()3()3()2()1()()(kcxkbxkaxkykcxkbxkaxkykcxkbxkaxkyncxnbxnaxny YORK UNIVERSITYCSE4210 X(3k) or x(3k-2)? 8 YORK UNIVERSITYCSE4210Complete Parallel System Serial to Parallel Converter MIMO SYSTEM Parallel to Serial y(n) Clock period Sampling period Clock period x(4k+3) x(4k+1) x(4k+2) x(4k) y(4k)y(4k+1)y(4k+2)y(4k+3) YORK UNIVERSITYCSE4210 T/4T/4 x(4k+3) x(4k+2) x(4k+1) x(4k) D y(n) T/4T/4 9 •Why use parallel processing? It increases •There is a limit for the use of pipelining, •Also, I/O usually imposes a bound on the YORK UNIVERSITYCSE4210 and parallel processing 10 YORK UNIVERSITYCSE4210Low Power Simple approximation for CMOSis the capacitance to beng could be used to minimize power or execution time. •What happens in case of M –pipelining?•Critical path is reduced by charge•If we keep the same charge ?,)()(2charge2chargePVVkVMCTVVkVCTtoopiptooseq 11 YORK UNIVERSITYCSE4210Low Power —Example D D x(n) m1 a1 YORK UNIVERSITYCSE4210 12 •What happen for •Total capacitance increased by •Same performance, increase T by •More time to charge charge ?,)()(2arg2chargePVVkVCTVVkVCLLTtooechpartooseq •Consider a 4-tap FIR filter shown in Fig. 3.18(a) •Assume Also that T=3.3V, C–What is the supply voltage –What is the power consumpti 13 YORK UNIVERSITYCSE4210 YORK UNIVERSITYCSE4210 14 YORK UNIVERSITYCSE4210Different Architecture