Don Porter 1 Representing Instructions Todays topics von Neumann model of a computer Instruction set architecture MIPS instruction formats Some MIPS instructions Reading PampH textbook Ch 2122 Ch 2526 ID: 756774
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Slide1
Instruction Sets, Episode 1
Don Porter
1Slide2
Representing Instructions
Today’s topicsvon Neumann model of a computerInstruction set architectureMIPS instruction formatsSome MIPS instructions
Reading
P&H textbook Ch. 2.1-2.2, Ch. 2.5-2.6
2Slide3
A General-Purpose Computer
The von Neumann Model
Many architectural models for a general-purpose computer have been explored
Most of today’s computers based on the model proposed by John von Neumann in the late 1940s
Its major components are:
3
Central
Processing Unit
Central Processing Unit (CPU): Fetches, interprets, and executes a specified set of operations called
Instructions
.
Main
Memory
Memory: storage of N
words
of W bits each, where W is a fixed architectural parameter, and N can be expanded to meet needs.
Input/
Output
I/O: Devices for communicating with the outside world.Slide4
Instructions and Programs
What are instructions?the words of a computer’s languageInstruction Setthe full vocabularyStored Program Concept
The idea that instructions and data of many types can be stored in memory as numbers, leading to the stored program computer
Distinct from “application-specific” hardware, which is “hardwired” to perform “fixed-function” processing on inputs
Distinct from punched tape computers (e.g., looms) where instructions were not stored, but streamed in one at a time
4Slide5
Anatomy of an Instruction
An instruction is a
primitive
operation
Instructions specify an operation and its operands
(the necessary variables to perform the operation)
Types of operands: immediate, source, and destination
add $t0, $t1, $t2
addi $t0, $t1, 1
Operation
Operands
(variables, arguments, etc.)
Source Operands
Destination Operand
Immediate Operand
$X is a convention to denote the contents of a “register”, which is a location inside the CPU. In contrast, immediate operands indicate the value itself
5Slide6
Meaning of an Instruction
Operations are abbreviated into
opcodes
(1-4 letters)
Instructions are specified with a very regular syntax
First an
opcode
followed by arguments
Usually (but not always) the destination is next, then sourceWhy this order? Arbitrary…… but analogous to high-level language like Java or C
add $t0, $t1, $t2
(
int
) t0 = t1 + t2
implies
The instruction syntax provides operands in the same order as you would expect in a statement from a high level language.
6Slide7
Being the Machine!
Instruction sequence
Instructions are executed sequentially from a list …
… unless some special instructions alter this flow
Instructions execute one after another
therefore, results of all previous instructions have been computed
$t0: 0
$t1: 6
$t2: 8
$t3: 10
Variables
add $t0, $t1, $t1
add $t0, $t0, $t0
add $t0, $t0, $t0
sub $t1, $t0, $t1
Instructions
12
24
48
42
What is this program doing?
7Slide8
What did this machine do?
Let’s repeat the simulation, this time using unknowns
CLASS: What is this machine doing?
Knowing what the program does allows us to write down its specification, and give it a meaningful name
8
$t0: w
$t1: x
$t2: y
$t3: z
Variables
add $t0, $t1, $t1
add $t0, $t0, $t0
add $t0, $t0, $t0
sub $t1, $t0, $t1
Instructions
2x
4x
8x
7x
times7:Slide9
Looping the Flow
Need something to change the instruction flow
“go back” to the beginning
a
jump
instruction with
opcode
‘j’the operand refers to a label of some other instructionfor now, this is a text label you assign to an instructionin reality, the text label becomes a numerical address
$t0: w
$t1: x
$t2: y
$t3: z
Variables
add $t0, $t1, $t1
add $t0, $t0, $t0
add $t0, $t0, $t0
sub $t1, $t0, $t1
Instructions
8x
7x
times7:
j times7
56x
49x
392x
343x
An infinite loopSlide10
Open Questions in our Simple Model
We will answer the following questions next
WHERE are INSTRUCTIONS stored?
HOW are instructions represented?
WHERE are VARIABLES stored?
How are labels associated with particular instructions?
How do you access more complicated variable types:
Arrays?
Structures?Objects?Where does a program start executing?How does it stop?
10Slide11
The Stored-Program Computer
The von Neumann model:Instructions and Data stored in a common memory (“main memory”)Sequential semantics: All instructions execute sequentially (or at least appear sequential to the programmer)
11
Key idea: Memory holds not only data, but
coded instructions
that make up a
program
.
Central
Processing Unit
Main Memory
instruction
instruction
instruction
data
data
data
CPU fetches and executes instructions from memory ...
The CPU is a hardware interpreter
Program
IS
simply data for this interpreter
Main memory: Single expandable resource pool
- constrains both data and program size
- don’
t need to make separate decisions of
how large of a program or data memory to buySlide12
Anatomy of a von Neumann Computer
Control
Unit
Data
Path
registers
MEMORY
control
status
instructions
data
PC
1101000111011
• INSTRUCTIONS coded in binary
• PROGRAM COUNTER or PC: Address of next instruction to be executed
• Control Unit has circuitry inside to translate instructions into control signals for data path
+1
R1
R2+R3
address
address
12
“Register File”
Register 0
Register 1
Register 31Slide13
Instruction Set Architecture (ISA)
Definition:The part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/OAn ISA includes a specification of the set of
opcodes
(machine language), and the native commands implemented by a particular processor
13Slide14
Instruction Set Architecture (ISA)
Encoding of instructions raises interesting choices...
Tradeoffs: performance, compactness, programmability
Complexity
How many different instructions? What level operations?
Level of support for particular software operations: array indexing, procedure calls,
“
polynomial evaluate
”, etc.“Reduced Instruction Set Computer” (RISC) philosophy: simple instructions, optimized for speedUniformityShould different instructions be same size?
Take the same amount of time to execute?
Trend favors uniformity
simplicity, speed, cost/power
Mix of Engineering & Art...Trial (by simulation) is our best technique for making choices!Our representative example: the MIPS architectureSlide15
The big picture
A few things to note:Memory is distinct from data pathRegisters are in data pathProgram is stored in memory
Control unit fetches instructions from memory
Control unit tells data path what to do
Data can be moved from memory to registers, or from registers to memory
All data processing (e.g., arithmetic) takes place within the data path
15
Control
Unit
Data
Path
registers
MEMORY
control
status
instructions
data
address
addressSlide16
MIPS Programming Model
a representative simple RISC machine
16
Processor State
(inside the CPU)
Main Memory
Fetch/Execute loop:
fetch
Mem[PC
]
PC = PC +
4
†
execute fetched instruction (may change PC!) repeat!
†
MIPS
uses byte memory addresses.
However, each instruction is 32-bits wide, and *must* be aligned on a multiple of 4 (word) address.
Each word contains four 8-bit bytes. Addresses of consecutive instructions (words) differ by 4.
00
PC
r0
r1
r2
...
r31
000000....0
32 bit
“
words
”
0
1
2
3
(4 bytes)
32 bit
“
words
”
0
31
next instruction
General Registers:
A small scratchpad
of frequently used
or temporary variables
In Comp 411 we’
ll use a clean and sufficient subset of the
MIPS-32 core Instruction set.
0
4
8
16
20
AddressesSlide17
Some MIPS Memory Nits
Memory locations are 32 bits wide
BUT, they are addressable in different-sized chunks
8-bit chunks (bytes)
16-bit chunks (shorts)
32-bit chunks (words)
64-bit chunks (longs/double)
We also frequently need
access to individual bits!(Instructions help w/ this)Every BYTE has a unique address (MIPS is a byte-addressable machine)Every instruction is one word
0
1
2
3456
7Addr
0:4:
8:12:
8
9
10
12121314
15
byte3 byte2 byte1 byte0
short2 short0
long0
long8
31 30 29 … … 4 3 2 1 0
17Slide18
MIPS Register Nits
There are 32 named registers [$0, $1, …. $31]
The operands of
all
ALU instructions are registers
This means to operate on a variables in memory you must:
Load the value/values from memory into a register
Perform the instruction
Store the result back into memoryGoing to and from memory can be expensive(4x to 20x slower than operating on a register)Net effect: Keep variables in registers as much as possible!Special purpose and conventions2 registers have specific “side-effects”(ex: $0 always contains the value ‘
0
’
… more later)4 registers dedicated to specific tasks by convention
26 available for general use, but constrained by convention18Slide19
MIPS Instruction Formats
All MIPS instructions fit into a single 32-bit wordEvery instruction includes various “fields”
:
a 6-bit operation or
“
OPCODE
”
specifies which operation to execute (fewer than 64)up to three 5-bit OPERAND fieldseach specifies a register (one of 32) as source/destination
embedded constantsalso called “literals” or “immediates”16-bits, 5-bits or 26-bits longsometimes treated as signed values, sometimes unsignedThere are three basic instruction formats:
R-type
, 3 register operands (2 sources, destination)
I-type
, 2 register operands, 16-bit constant
OP
r
s
r
t
r
d
OP
r
s
r
t
16-bit constant
func
shamt
J-type
, no register operands, 26-bit constant
OP
26-bit constant Slide20
MIPS ALU Operations
Sample coded operation: ADD instruction
What
we
prefer to write:
add $10, $11, $9
(
“assembly language”)add rd, rs, rt:
“
Add the contents of rs to the contents of rt; store the result in rd
”
Reg[rd] = Reg[rs] + Reg[rt]arithmetic: add, sub, addu, subu
compare: slt, sltulogical: and, or, xor, norshift: sll, srl, sra, sllv, srav, srlv
Similar instructions for other ALU operations:
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
op = 0x00
dictating an
ALU function
rs = 11
Reg[11]
source
rd = 10
Reg[10]
destination
rt = 9
Reg[9]
source
unused
fields are
set to
‘
0
’
func = 0x20
dictating an
add
References to register contents are prefixed by a
“
$
”
to distinguish them from constants or memory addresses
R-type:
The convention with MIPS assembly language is to specify the destination operand first, followed by source operands.
20Slide21
Shift operations
Shifting is a common operationapplied to groups of bits
used for alignment
used for
“
short cut
”
arithmetic operations
X << 1 is often the same as 2*XX >> 1 can be the same as X/2For example:X = 2010 = 000101002Left Shift:(X << 1) = 001010002 = 4010
Right Shift:(X >> 1) =
0
00010102 = 10
10Signed or “Arithmetic” Right Shift:(-X >>> 1) = (111011002 >>> 1) = 111101102 = -1010Slide22
MIPS Shift Operations
Sample coded operation: SHIFT LOGICAL LEFT instruction
Assembly:
sll $2, $2, 4
sll rd, rt, shamt
:
“
Shift the contents of
rt to the left by shamt
; store the result in rd”
Reg
[
rd] = Reg[rt] << shamt
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
op = 0x00
dictating an
ALU function
unused
set to
‘
0
’
rd = 2
Reg[2]
destination
rt = 2
Reg[2]
source
shamt = 4 dictates a shift of 4-bits
func = 0x00
dictating an
sll
R-type:
22Slide23
MIPS Shift Operations
Sample coded operation: SLLV (SLL Variable)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
op = 0x00
dictating an
ALU function
shift
amount
in rs
rd = 2
Reg[2]
destination
rt = 2
Reg[2]
source
unused set to ‘0’
func = 0x04
dictating an
sllv
Assembly:
sllv $2, $2, $8
sllv rd, rt, rs
:
“
Shift the contents of
rt
left by the contents of
rs
; store the result in
rd
”
Reg[rd]
=
Reg[rt] << Reg[rs]
This is peculiar syntax for MIPS, in this ALU instruction the rt operand precedes the rs operand. Usually, it
’
s the other way around
R-type:
Different flavor:
Shift amount is not in instruction, but in a register
23Slide24
MIPS ALU Operations with Immediate
addi
instruction: adds register contents, signed-constant:
Symbolic version:
addi $9, $11, -3
“
Add the contents of rs to const; store result in rt
”
OP = 0x08, dictating addi
rs = 11, Reg[11]
source
rt = 9, Reg[9] destination
Reg[rt]
=
Reg[rs] + sxt(imm)
arithmetic:
addi
,
addiu
compare:
slti, sltiulogical: andi, ori, xori, lui
Similar instructions for other ALU operations:
constant field, indicating -3 as second operand
(sign-extended!)
addi rt, rs, imm
:
0
0
1
0
0
0
0
1
0
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Immediate values are sign-extended for arithmetic and compare operations, but not for logical operations.
I-type:
24Slide25
Why Built-in Constants? (Immediate)
Where are constants/immediates useful?SMALL constants used frequently (50% of operands)In a C compiler (gcc) 52% of ALU operations use a constant
In a circuit simulator (spice) 69% involve constants
e.g., B = B + 1; C = W & 0x00ff; A = B + 0;
Examples:
addi
$29, $29, 4
slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4
25Slide26
First MIPS Program (fragment)
Suppose you want to compute the expression: f = (g + h) – (i + j)
where variables f, g, h,
i
, and j are assigned to registers $16, $17, $18, $19, and $20 respectively
what is the MIPS assembly code?
Questions to answer:
How did these variables come to reside in registers?
Answer: We need more instructions which allow data to be explicitly loaded from memory to registers, and stored from registers to memoryadd $8,$17,$18 # (g + h)add $9,$19,$20 # (i + j)sub $16,$8,$9 # f = (g + h) – (i + j)
26Slide27
MIPS Register Usage Conventions
Some MIPS registers assigned to specific usesby convention, so programmers can combine code pieceswill cover the convention later$0 is hard-wired to the value 0Slide28
Continue next lecture…
More instructionsaccessing memorybranches and jumpslarger constantsmultiply, divideetc.
28