Virtuoso Schematic Composer User GuideUnderstanding Connectivity and N - PDF document

Virtuoso Schematic Composer User GuideUnderstanding Connectivity and Naming Conventions April 2001111Product Version 4.4.6 The ordering of the bits in a bus is important when you are connecting the bus to a pin thathas a width greater than 1.Evaluating Vector Expressions in Multiple-Bit Wire NamesThe system evaluates vector expressions in multiple-bit wire names as follows:The vector expression names a 2-bit bus containingThe vector expression names a 2-bit bus containingThe vector expressions are equivalent names thatgenerate a 4-bit bus containingIf the lower bound is larger than the upper bound, the editor generates the bit numbers indescending order, as follows:The vector expression generates a 3-bit bus that containsUsing PreÞx Repeat Operators in Multiple-Bit Wire NamesAmultiple-bitwirenamecanbeabundle,abus,oracombinationofthetwo.Youcanimprovereadability in your designs by shortening multiple-bit wire names.Youcanrepeatasinglesignalname,agroupofsignalnames,oravectortermanynumberoftimesinthewirenamebyplacingapreÞxrepeatoperatorinfrontofthename,where is a positive integer that deÞnes the number of times to repeat each bit in the vector term.Use the preÞx repeat operator to repeat a single-signal name. The followingequivalent wire names both name the same four-bit wire:UsethepreÞxrepeatoperatorandparenthesestorepeatagroupofsignalnames.The following two wire names are equivalent:Use combinations of the preÞx repeat operatorparentheticalexpressionstoanyrequireddepth.Theeditorexpandsnestedexpressionsfrom the innermost expression outward. For example, a name with the expression expands to Virtuoso Schematic Composer User GuideUnderstanding Connectivity and Naming Conventions April 2001113Product Version 4.4.6 Hierarchical Pin NamesIf you are designing a multisheet schematic, your sheets contain hierarchical pins andoffsheet pins.Hierarchicalpinsarepinsthatalsoappearonthesymbolofthedesign.Thehierarchicalpinsfrom each sheet become the hierarchical pins of the multisheet.Offsheetpinsconnectsignalsacrossthesheetsofamultisheetschematiconly.Usethesamename for the offsheet pins on each sheet.Ifyouwantasignaltoappearonamultiplesheetthatisalsoexportedbyahierarchicalpin,placeahierarchialpinfortheÞrstusageandoffsheetpinsonothersheets.Donotplacemorethan one hierarchical pin with the same name in a multisheet design. xpression. For example, expands to thesefour pins: �:70;IO �:70;OUT2 �:70;A Hierarchical pin �:70;IO �:70;OUT2 �:70;A Hierarchical pin Virtuoso Schematic Composer User GuideUnderstanding Connectivity and Naming Conventions April 2001115Product Version 4.4.6 The following Þgure shows how to tap pins in a design.In the example above, the wire namedandconnectsafour-bitbuscalledtotheinputoftheinverter(aniterated instance). pin and connects a four-bit bus gate (also an iterated instance).Ifyoudonotapplyanametoanetthatisattachedtoapin,theeditorgivesthenetthesamename as the pin. For example, the wire that connects the output of thePatchcord Connections and Patchcord NamingConventionsschPatchExpr connection expression (value) for patchcords has the following form: :40;invnand2YABOUTPUT:00; AY�:30;:00; �:30;I1�:30;I4 �:30;OUTPUT Hierarchical pin Hierarchical pin AB0=0