Fig1Thresholdvoltagedistributionin2bitMLCNANDashStoreddatavaluesarerepresentedasthetupleLSBMSBNANDFlashBlockOrganizationANANDashmemorychipisorganizedasthousandsoftwodimensionalarraysofash ID: 257722
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Weexploitthesestudiesontherelationbetweenthereaddisturbeffectandthepass-throughvoltage(Vpass),todesigntwomechanismsthatreducetheimpactofreaddisturb.First,weproposealow-costdynamicmechanismcalledVpassTuning,which,foreachblock,ndsthelowestpass-throughvoltagethatretainsdatacorrectness.VpassTuningextendsashendurancebyexploitingthendingthatalowerVpassreducesthereaddisturberrorcount(Sec.4).Second,weproposeReadDisturbRecovery(RDR),amechanismthatexploitsthedifferencesinthesusceptibilityofdifferentcellstoreaddisturbtoextendtheeffectivecorrectioncapabilityoferror-correctingcodes(ECC).RDRprobabilisticallyidentiesandcorrectscellssusceptibletoreaddisturberrors(Sec.5).Toourknowledge,thispaperisthersttomakethefollowingcontributions:Weperformadetailedexperimentalcharacterizationofhowthethresholdvoltagedistributionsforashcellsgetdistortedduetothereaddisturbphenomenon.Weproposeanewtechniquetomitigatetheerrorsthatareinducedbyreaddisturbeffects.Thistechniquedy-namicallytunesthepass-throughvoltageonaper-blockbasistominimizereaddisturberrors.WeevaluatetheproposedreaddisturbmitigationtechniqueonavarietyofrealworkloadI/Otraces,andshowthatitincreasesashmemoryenduranceby21%.Weproposeanewmechanismthatcanprobabilisticallyidentifyandcorrectcellssusceptibletoreaddisturberrors.Thismechanismcanreducetheashmemoryrawbiterrorratebyupto36%.2.BackgroundandRelatedWorkInthissection,werstprovidesomenecessarybackgroundonstoringandreadingdatainNANDashmemory.Next,wediscussreaddisturb,atypeoferrorinducedbyneighboringreadoperations,anddescribeitsunderlyingcauses.2.1.DataStorageinNANDFlashNANDFlashCellThresholdVoltageRange.Aashmemorycellstoresdataintheformofathresholdvoltage,thelowestvoltageatwhichtheashcellcanbeswitchedon.AsillustratedinFig.1,thethresholdvoltage(Vth)rangeofa2-bitMLCNANDashcellisdividedintofourregionsbythreereferencevoltages,Va,Vb,andVc.Theregioninwhichthethresholdvoltageofaashcellfallsrepresentsthecell'scurrentstate,whichcanbeER(orerased),P1,P2,orP3.Eachstatedecodesintoa2-bitvaluethatisstoredintheashcell(e.g.,11,10,00,or01).Werepresentthis2-bitvaluethroughoutthepaperasatuple(LSB,MSB),whereLSBistheleastsignicantbitandMSBisthemostsignicantbit.Notethatthethresholdvoltageofallashcellsinachipisboundedbyanupperlimit,Vpass,whichisthepass-throughvoltage. Fig.1.Thresholdvoltagedistributionin2-bitMLCNANDash.Storeddatavaluesarerepresentedasthetuple(LSB,MSB).NANDFlashBlockOrganization.ANANDashmemorychipisorganizedasthousandsoftwo-dimensionalarraysofashcells,calledblocks.Withineachblock,asillustratedinFig.2a,allthecellsinthesamerowshareawordline(WL),whichtypicallyspans32Kto64Kcells.TheLSBsstoredinawordlineformtheLSBpage,andtheMSBsstoredinawordlineformtheMSBpage.Withinablock,allcellsinthesamecolumnareconnectedinseriestoformabitlineorstring(BLinFig.2a).Allcellsinabitlineshareacommongroundononeend,andacommonsenseamplierontheotherforreadingthethresholdvoltageofoneofthecellswhendecodingdata. Fig.2.(a)NANDashblockstructure.(b/c)Diagramsofoatinggatetransistorswhendifferentvoltages(Vpass/Vref)areappliedtothewordline.NANDFlashReadOperation.ANANDashreadoperationisperformedbyapplyingareadreferencevoltageVrefoneormoretimestothewordlinethatcontainsthedatatoberead,andsensingwhetherthecellsonthewordlineareswitchedonornot.TheappliedVrefischosenfromthereferencevoltagesVa,Vb,andVc,andchangesbasedonwhichpage(i.e.,LSBorMSB)wearecurrentlyreading.ToreadanLSBpage,onlyonereadreferencevoltage,Vb,needstobeapplied.IfacellisintheERorP1state,itsthresholdvoltageislowerthanVb,henceitisswitchedon.IfacellisintheP2orP3state,itsthresholdvoltageishigherthanVb,andthecellisswitchedoff.ThesenseampliercanthendeterminewhetherthecellisswitchedonorofftoreadthedatainthisLSBpage.ToreadtheMSBpage,tworeadreferencevoltages,VaandVc,needtobeappliedinsequencetothewordline.IfacellturnsoffwhenVaisappliedandturnsonwhenVcisapplied,wedeterminethatthecellcontainsathresholdvoltageVthwhereVaVthVc,indicatingthatitisineithertheP1orP2stateandholdsanMSBvalueof0(seeFig.1).Otherwise,ifthecellisonwhenVaisappliedoroffwhenVcisapplied,thecellisintheERorP3state,holdinganMSBvalueof1.Aswementionedbefore,thecellsonabitlineareconnectedinseriestothesenseamplier.Inordertoreadfromasinglecellonthebitline,alloftheothercellsonthesamebitlinemustswitchedontoallowthevaluebeingreadtopropagatethroughtothesenseamplier.Wecanachievethisbyapplyingthepass-throughvoltageontothewordlinesofunreadcells.Modernashmemoriesguaranteethatallunreadcellsarepassedthrough(i.e.,themaximumpossiblethresholdvoltage,Vpass,isappliedtothecells)tominimizeerrorsduringthereadoperation.Wewillshow,inSec.3.6,thatthischoiceisconservative:applyingasingleworst-casepass-throughvoltagetoallcellsisnotnecessaryforcorrectoperation.2.2.ReadDisturbReaddisturbisawell-knownphenomenoninNANDashmemory,wherereadingdatafromaashcellcancausethethresholdvoltagesofother(unread)cellsinthesameblocktoshifttoahighervalue[2,11,14,15,24,33].Whileasinglethresholdvoltageshiftissmall,suchshiftscanaccumulateover2 Fig.3.(a)Thresholdvoltagedistributionofallstatesbeforeandafterreaddisturb;(b)ThresholdvoltagedistributionbetweenerasedstateandP1state.blocktodeterminehowmuchthethresholdvoltageforeachcellshifted.Werepeatthisprocesstomeasurethedistributionshiftoveranincreasingnumberofreaddisturboccurrences.Fig.3ashowsthedistributionofthethresholdvoltagesforcellsinaashblockafter0,250K,500K,and1millionreadoperations.Fig.3bzoomsinonthistoillustratethedistributionforvaluesintheERstate.3Weobservethatstateswithlowerthresholdvoltagesareslightlymorevulnerabletoshiftsthanstateswithhigherthresholdvoltages.Thisisduetoapplyingthesamevoltage(Vpass)toallcellsduringareaddisturboperation,regardlessoftheirthresholdvoltages.Alowerthresholdvoltageonacellinducesalargervoltagedifference(Vpass�Vth)throughthetunnel,andinturngeneratesastrongertunnelingcurrent,makingthecellmorevulnerabletoreaddisturb.ThedegreeofthethresholdvoltageshiftisbrokendownfurtherinFig.4,wherewegroupcellsbytheirinitially-programmedstate.Theguredemonstratestheshiftinmeanthresholdvoltageforeachgroup,asthenumberofreaddisturboccurrencesincreasesduetomorereadsbeingperformedtotheblockovertime.Fig.4ashowsthatforcellsintheERstate,thereisasystematicshiftofthecellthresholdvoltagedistributiontotheright(i.e.,tohighervalues),demonstratingasignicantchangeasaresultofreaddisturb.Incontrast,theincreasesforcellsstartingintheP1(Fig.4b)andP2(Fig.4c)statesaremuchmorerestricted,showinghowthereaddisturbeffectbecomeslessprominentasVthincreases(asexplainedabove).FortheP3state,asshowninFig.4d,weactuallyobserveadecreaseinthemeanVth.Thisdecreaseisduetotheeffectsofretentionlossarisingfromchargeleakage.Asdataisheldwithineachashcell,thestoredchargeslowlyleaksovertime,withadifferentrateofleakageacrossdifferentashcellsduetobothprocessvariationandunevenwear.ForcellsintheP3state,theeffectsofreaddisturbareminimal,andsoweprimarilyseetheretention-causeddropinthresholdvoltage(whichissmall).4Forcellsstartinginotherstates,thereaddisturbphenomenonoutweighsleakageduetoretentionloss,resultinginincreasesintheirmeans.Again,cellsintheERstatearemostaffectedbyreaddisturb.Fig.5showsthechangeinthestandarddeviationofthethresholdvoltage,againgroupedbytheinitialthresholdvoltageofthecell,afteranincreasingnumberofreaddisturboccur-rences.ForcellsstartingintheP1,P2,andP3states,weobserveanincreasedspreadinthethresholdvoltagedistribution,aresultofbothunevenreaddisturbeffectsandunevenretentionloss.FortheERstate,weactuallyobserveaslightreductioninthedeviation,whichisaresultofourmeasurementlimitations: 3Fornow,weuseaashblockthathasexperienced8,000program/erase(P/E)cycles.WewillshowsensitivitytoP/EcyclesinSec.3.3.4Retentionlosseffectsareobservableintheseresultsbecauseittakesapproximatelytwohourstoperform200Kreadoperations,duetothelatencybetweentheashdeviceandtheFPGAhostsoftware. Fig.4.Meanvalueofnormalizedcellthresholdvoltage,asthereaddisturbcountincreasesovertime.Distributionsareseparatedbycellstates. Fig.5.Standarddeviationofnormalizedcellthresholdvoltage,asthereaddisturbcountincreasesovertime.Distributionsareseparatedbycellstates.cellsintheERstateoftenhaveanegativeVth,butwecanonlymeasurenon-negativevaluesofVth,sothemajorityofthesecellsdonotshowupinourdistributions.Weconcludethatthemagnitudeofthethresholdvoltageshiftforacellduetoreaddisturb(1)increaseswiththenumberofreaddisturboperations,and(2)ishigherifthecellhasalowerthresholdvoltage.3.3.EffectofReadDisturbonRawBitErrorRateNowthatweknowhowmuchthethresholdvoltageshiftsduetoreaddisturbeffects,weaimtorelatetheseshiftstotherawbiterrorrate(RBER),whichreferstotheprobabilityofreadinganincorrectstatefromaashcell.WeseethatforagivenamountofP/Ecyclewearonablock,therawbiterrorrateincreasesroughlylinearlywiththenumberofreaddisturboperations.Fig.6showstheRBERoveranincreasingnumberofreaddisturboperationsfordifferentamountsofP/Ecyclewearonashblocks.EachlevelshowsalinearRBERincreaseasthereaddisturbcountincreases.4 Ourmechanismalsorequiressomeextrastorageforeachblock,requiringonebytetorecordour8-bittunedVpasssettingandasecondbytetostorethepagenumberofthepredictedworst-casepage(weassumethateachashblockcontains256pages).Forourassumed512GBSSD,thisusesatotalof655362B=128KBstorageoverhead.4.6.MethodologyWeevaluateVpassTuningwithI/Otracescollectedfromawiderangeofrealworkloadswithdifferentusecases[17,20,27,31,34],listedinTable2.Tocomputeashchipendurance(thenumberofP/Ecyclesatwhichthetotalerrorratebecomestoolarge,resultinginanuncorrectablefailure)forboththebaselineandtheproposedVpassTuningtechnique,werstndtheblockwiththehighestnumberofreadsforeachtrace(asthisblockconstrainsthelifetime),aswellastheworst-casereaddisturbcountforthatblock.Next,weexploitourresultsfromSec.3.7(Table1)todeterminetheequivalentreaddisturbcountfortheblockwiththeworst-casereaddisturbcountafterVpassTuning.Finally,weuseourresultsfromSec.3.3(Fig.6)todeterminetheendurance.Ourresultsfaithfullytakeintoaccounttheeffectofallsourcesofasherrors,includingprocessvariation,P/Ecycling,cell-to-cellprograminterference,retention,andreaddisturberrors.Table2.Simulatedworkloadtraces. TraceSourceMax.7-DayReadDisturbCounttoaSingleBlock homesFIU[20]511web-vmFIU[20]2416mailFIU[20]23612mdsMSR[27]36529rsrchMSR[27]39810prnMSR[27]40966webMSR[27]41816stgMSR[27]49680tsMSR[27]54652projMSR[27]64480srcMSR[27]66726wdevMSR[27]66800usrMSR[27]154464postmarkPostmark[17]308226hmMSR[27]343419cello99HPLabs[31]363155websearchUMass[34]611839nancialUMass[34]1729028prxyMSR[27]2950196 4.7.EvaluationFig.14plotstheP/Ecycleenduranceforthesimu-latedtraces.Forread-intensiveworkloads(postmark,nancial,websearch,hm,prxy,andcello99),theoverallashenduranceimprovessignicantlywithVpassTuning.Table2liststhehighestreaddisturbcountforanyoneblockwithinarefreshinterval.Weobservethatworkloadswithhigherreaddisturbcountsseeagreaterimprovement(inFig.14).AswecanseeinFig.14,theabsolutevalueofendurancewithVpassTuningissimilaracrossallworkloads.Thisisbecausetheworkloadsareapproachingtheminimumpossiblenumberofreaddisturberrors,andareclosetothemaximumenduranceimprovementsthatreaddisturbmitigationcanachieve.Onaverageacrossallofourworkloads,overallashenduranceimprovesby21.0%withVpassTuning.WeconcludethatVpassTuningeffectivelyimprovesashendurancewithoutsignicantlyaffectingashperformanceorhardwarecost. Fig.14.EnduranceimprovementwithVpassTuning.5.ReadDisturbOrientedErrorRecoveryInthissection,weintroduceanothertechniquethatexploitsourobservationsfromSec.3,calledReadDisturbRecovery(RDR).ThistechniquerecoversfromanECC-uncorrectableasherrorbycharacterizing,identifying,andselectivelycor-rectingcellsmoresusceptibletoreaddisturberrors.85.1.MotivationInSec.3.2,weobservedthatthethresholdvoltageshiftduetoreaddisturbisthegreatestforcellsinthelowestthresholdvoltagestate(i.e.,theerasedstate).InFig.15,weshowexamplethresholdvoltagedistributionsfortheerasedandP1states,andillustratetheoptimalreadreferencevoltage(Va)betweenthesetwostates,bothbeforeandafterreaddisturb.Beforereaddisturboccurs,thetwodistributionsareseparatedbyacertainvoltagemargin,asillustratedinFig.15a.Inthiscase,Vafallsinthemiddleofthismargin.Aftersomenumberofreaddisturboperations,therelativethresholdvoltagedistributionsoftheerasedstateandtheP1stateshiftclosertoeachother,eliminatingthevoltagemarginandeventuallycausingthedistributionstooverlap,asillustratedinFig.15b.Inthiscase,theoptimalValiesattheintersectionofthetwodistributions,asitminimizestherawbiterrors. Fig.15.Vthdistributionsbeforeandafterreaddisturb.EvenwhentheoptimalVaisappliedafterenoughreaddisturbs,somecellsintheerasedstatearemisreadasbeingintheP1state(shownasbluecells),whilesomecellsintheP1statearemisreadasbeingintheerasedstate(shownasredcells).Inthesecases,errorsoccur,and,aswehavementionedbefore,consumesomeoftheECCerrorcorrectioncapability.Eventually,astheseerrorsaccumulatewithinapageandexceedthetotalECCcorrectioncapability,theECCcannolongercorrectthem,resultinginanuncorrectableasherror.Anuncorrectableasherroristhemostcriticaltypeoferrorbecause(1)itdeterminestheashlifetime,whichistheguaranteedtimeaashdevicecanbeusedwithoutexceedingaxedrateofuncorrectableerrors,and(2)itmayresultinthepermanentlossofimportantuserdata.Aswementionedbefore,rawbiterrorsareacombinationofreaddisturberrorsandothererrortypes,suchasprogramerrorsandretentionerrors.IfweweresomehowabletocorrectevenafractionofthereaddisturberrorswithamechanismotherthanECC,thosenow-removederrorswouldnolongerconsumepartofthelimitedECCcorrectioncapability.Asaresult,thetotalamountofrawbiterrorsthattheashdevice 8RDRcanperformerrorrecoveryeitheronlineorofine.Weleavethedetailedexplorationofthebenetsandtrade-offsofonlinevs.ofinerecoverytofuturework.10 Step3:Induceadditionalreaddisturbstothispage,byrepeat-edlyreadingfromanotherpageinthesameblock100Ktimes.Step4:Scanandsavethethresholdvoltagesofthecellsinthefailedpageagain(sameasStep2)toanotherblock.Step5:Selectthecellswiththresholdvoltagesclosetoareadreferencevoltage(Vref�=2VthVref+=2,andVrefissettoVa,Vb,orVc).Calculatethechangeinthresholdvoltageforthesecellsbefore(Step2)andafter100Kreaddisturbs(Step4).SetVrefequaltothemeanofthesedifferences.Step6:UsingtheVrefvaluefromStep5,predictacellwhosethresholdvoltagechangesbymorethanVrefasdisturb-prone,andassumeitwasoriginallyprogrammedintothelowerofthetwopossiblecellstates.PredictacellwhosethresholdvoltagechangesbylessthanVrefasdisturb-resistant,andassumeitwasoriginallyinthehighervoltagestate(seeSec.5.2).Usingthesestateassumptions,attempttorecoverthefailedpageusingECC.5.4.EvaluationWeevaluatehowtheoverallRBERchangeswhenweuseRDR.Fig.17showsexperimentalresultsforerrorrecoveryinaashblockwith8,000P/Ecyclesofwear.WhenRDRisapplied,thereductioninoverallRBERgrowswiththereaddisturbcount,fromafewpercentforlowreaddisturbcountsupto36%for1millionreaddisturboperations.Asdataex-periencesagreaternumberofreaddisturboperations,thereaddisturberrorcountcontributestoasignicantlylargerportionofthetotalerrorcount,whichourrecoverymechanismtargetsandreduces.WethereforeconcludethatRDRcanprovidealargeeffectiveextensionoftheECCcorrectioncapability. Fig.17.Rawbiterrorratevs.numberofreaddisturboperations,withandwithoutRDR,foraashblockwith8,000P/Ecyclesofwear.6.ConclusionThispaperprovidestherstdetailedexperimentalcharac-terizationofreaddisturberrorsfor2Y-nmMLCNANDashmemorychips.Wendthatbiterrorsduetoreaddisturbaremuchmorelikelytotakeplaceincellswithlowerthresholdvoltages,aswellasincellswithgreaterwear.Wealsondthatreducingthepass-throughvoltagecaneffectivelymitigatereaddisturberrors.Usingtheseinsights,wepropose(1)amitigationmechanism,calledVpassTuning,whichdynamicallyadjuststhepass-throughvoltageforeachashblockonlinetominimizereaddisturberrors,and(2)anerrorrecoverymechanism,calledReadDisturbRecovery,whichexploitsthedifferencesinsusceptibilityofdifferentcellstoreaddisturb,toprobabilisticallycorrectreaddisturberrors.Wehopethatourcharacterizationandanalysisofthereaddisturbphenomenonenablesthedevelopmentofothererrormitigationandtolerancemechanisms,whichwillbecomeincreasinglynecessaryascontinuedashmemoryscalingleadstogreatersusceptibilitytoreaddisturb.WealsohopethatourresultswillmotivateNANDashmanufacturerstoaddpass-throughvoltagecontrolstonext-generationchips,allowingashcontrollerdesignerstoexploitourndingsanddesigncontrollersthattoleratereaddisturbmoreeffectively.AcknowledgmentsWethanktheanonymousreviewersfortheirfeedback.ThisworkispartiallysupportedbytheIntelScienceandTechnologyCenter,theCMUDataStorageSystemsCenter,andNSFgrants0953246,1065112,1212962,and1320531.References[1]Y.Caietal.,“FPGA-BasedSolid-StateDrivePrototypingPlatform,”inFCCM,2011.[2]Y.Caietal.,“ErrorPatternsinMLCNANDFlashMemory:Measure-ment,Characterization,andAnalysis,”inDATE,2012.[3]Y.Caietal.,“ThresholdVoltageDistributioninNANDFlashMemory:Characterization,Analysis,andModeling,”inDATE,2013.[4]Y.Caietal.,“DataRetentioninMLCNANDFlashMemory:Char-acterization,Optimization,andRecovery,”inHPCA,2015.[5]Y.Caietal.,“ProgramInterferenceinMLCNANDFlashMemory:Characterization,Modeling,andMitigation,”inICCD,2013.[6]Y.Caietal.,“FlashCorrectandRefresh:RetentionAwareManagementforIncreasedLifetime,”inICCD,2012.[7]Y.Caietal.,“ErrorAnalysisandRetention-AwareErrorManagementforNANDFlashMemory,”IntelTechnologyJournal(ITJ),2013.[8]Y.Caietal.,“NeighborCellAssistedErrorCorrectioninMLCNANDFlashMemories,”inSIGMETRICS,2014.[9]J.ChaandS.Kang,“DataRandomizationSchemeforEnduranceEnhancementandInterferenceMitigationofMultilevelFlashMemoryDevices,”ETRIJournal,2013.[10]CharlesManning,“YaffsNANDFlashFailureMitigation,”2012.http://www.yaffs.net/sites/yaffs.net/les/YaffsNandFailureMitigation.pdf[11]J.Cooke,“TheInconvenientTruthsofNANDFlashMemory,”FlashMemorySummit,2007.[12]R.H.FowlerandL.Nordheim,“ElectronEmissioninIntenseElectricFields,”inProceedingsoftheRoyalSocietyofLondonA:Mathemat-ical,PhysicalandEngineeringSciences,1928.[13]H.H.Frostetal.,“EfcientReductionofReadDisturbErrorsinNANDFlashMemory,”USPatentNo.7818525.2010.[14]L.M.Gruppetal.,“CharacterizingFlashMemory:Anomalies,Obser-vations,andApplications,”inMICRO,2009.[15]K.Haetal.,“ARead-DisturbManagementTechniqueforHigh-DensityNANDFlashMemory,”inAPSys,2013.[16]JEDECSolidStateTechnologyAssn.,“FailureMechanismsandMod-elsforSemiconductorDevices,”Doc.No.JEP122G.2011.[17]J.Katcher,“Postmark:ANewFileSystemBenchmark,”NetworkAppliance,Tech.Rep.TR3022,1997.[18]C.Kimetal.,“A21nmHighPerformance64GbMLCNANDFlashMemorywith400MB/sAsynchronousToggleDDRInterface,”JSSC,2012.[19]Y.Kimetal.,“FlippingBitsinMemoryWithoutAccessingThem:AnExperimentalStudyofDRAMDisturbanceErrors,”inISCA,2014.[20]R.KollerandR.Rangaswami,“I/ODeduplication:UtilizingContentSimilaritytoImproveI/OPerformance,”TOS,2010.[21]S.LinandD.J.Costello,ErrorControlCoding.PrenticeHall,2004.[22]R.-S.Liuetal.,“Duracache:ADurableSSDCacheUsingMLCNANDFlash,”inDAC,2013.[23]R.-S.Liuetal.,“OptimizingNANDFlash-BasedSSDsviaRetentionRelaxation,”inFAST,2012.[24]N.Mielkeetal.,“BitErrorRateinNANDFlashMemories,”inIRPS,2008.[25]V.Mohanetal.,“reFreshSSDs:EnablingHighEndurance,LowCostFlashinDatacenters,”Univ.ofVirginia,Tech.Rep.CS-2012-05,2012.[26]V.Mohanetal.,“HowILearnedtoStopWorryingandLoveFlashEndurance,”inHotStorage,2010.[27]D.Narayananetal.,“Writeoff-Loading:PracticalPowerManagementforEnterpriseStorage,”TOS,2008.[28]Y.Panetal.,“Quasi-NonvolatileSSD:TradingFlashMemoryNon-volatilitytoImproveStorageSystemPerformanceforEnterpriseAp-plications,”inHPCA,2012.[29]K.-T.Parketal.,“A7MB/s64Gb3-Bit/CellDDRNANDFlashMemoryin20nm-NodeTechnology,”inISSCC,2011.[30]R.Smith,“SSDMovingRapidlytotheNextLevel,”FlashMemorySummit,2014.[31]StorageNetworkIndustryAssn.,“IOTTARepository:Cello1999.”http://iotta.snia.org/traces/21[32]T.SugaharaandT.Furuichi,“MemoryControllerforSuppressingReadDisturbWhenDataIsRepeatedlyReadOut,”USPatentNo.8725952.2014.[33]K.Takeuchietal.,“ANegativeVthCellArchitectureforHighlyScalable,ExcellentlyNoise-Immune,andHighlyReliableNANDFlashMemories,”IEEEJournalofSolid-StateCircuits,1999.[34]Univ.ofMassachusetts,“Storage:UMassTraceRepository.”http://tinyurl.com/k6golon12