RDHC MIDDLEWARE a software execution platform for corarhdc oNbOARD computer Author MAXIME GUIMARD Presenter Patricia Lopez Cueva GR740 USER Day 2019 28112019 00050011485879 ID: 1045668
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1. Compact Reconfigurable avionics –RDHC MIDDLEWARE: a software execution platform for cora-rhdc oN-bOARD computerAuthor: MAXIME GUIMARDPresenter: Patricia Lopez CuevaGR740 USER Day 201928/11/20190005-0011485879
2. 28/11/2019TABLE OF CONTENTSOverview of CoRA-RDHC study1Overview of CoRA-RDHC OBC2Overview of CoRA-RDHC SW3GR740 HW Experience4GR740 Coding Experience5GR740 Debug Experience60005-0011485879
3. CoRA-RDHC studyOverview28/11/20190005-0011485879
4. Design and manufacture an OBC SYSTEM hosting:A high performance microprocessor and high capacity reconfigurable FPGAsThe associated Elegant Bread Board (EBB) Standardised interfaces (Mil1553B, CAN, SpaceWire) to be used directly with digital devices or as a proxy toward analog interface devicesThis module acts as the HW execution platform for the “Compact Reconfigurable Avionics”Identify, procure and delivery a suitable SW execution platform for the development:Boot Software for the CRDHCMiddleware Software execution platform encompassing: Board Support Package and device drivers (HDSW), PUS library and FPGA reconfiguration Software CoRA-RDHC study - Objective 28/11/20190005-0011485879
5. ESATechnical Officer: Jørgen Ilstad, TEC-EDD –> EOP-PPECobham Gaisler AB, Sweden (prime)Responsible for the development of hardware, VHDL design, boot software and driversThales Alenia Space FranceResponsible for middleware software design and SW integrationThales Alenia Space España S.A., SpainResponsible for FPGA reconfiguration codeAirbus Defence & Space, FranceContribution to the systems analysis and trade-off, requirements and system architectureRDHC TEAM- ORGANISATION28/11/20190005-0011485879
6. CoRA-RDHC On BOARD COMPUTEROverview28/11/20190005-0011485879
7. RDHC OBC CONCEPT28/11/20190005-0011485879
8. RDHC OBC CONCEPT (BB version)28/11/20190005-0011485879
9. RDHC OBC CONCEPT (EBB VERSION)28/11/20190005-0011485879
10. CoRA-RDHC SOFTWAREOverview28/11/20190005-0011485879
11. RHDC MIDDLEWARE(1) FRAMEWORK = SW EXECUTION PLATFORM + SW building environnement Relying on:RTEMS 5.1 SMPRDHC BOOTRDHC BSP AND DRIVERS (HDSW)RDHC RECONFIGURATION ENGINE: NG MEDIUM FPGA MANAGEMENTLVCUGEN LIBPUS from CNESRDHC MIDDELWARE(2) gathering all previous SW (but the BOOT). Compliant to ESA BOOT standard(1): middle layer between HW and Applicative SW. The framework encompass all SW components and the building environment(2): SW glue in the middle of other SW piecesCoRA-RDHC SOFTWARE OVERVIEW- SOFTWARE EXECUTION PLATFORM28/11/20190005-0011485879
12. GR740 HW Experience28/11/20190005-0011485879
13. ProsBreakthrough for performances Core Level 3X times a LEON3FT @100MHZ (DMIPS test)Allows integration of computing intensive algorithmsAt Memory & cache levelL2 cache issue is now correctedSDRAM supported enabling larger SW imagesHigh speed SPW with router and timecodeReady for new high performances SpW-based OBCFulfill SPECIAL space requirementsTimecodes => Time synchronization and OBTSupport of atomic accesses on GPIOSupport current avionic buses (UART/CAN/1553/SPW)Opportunity to command future SpaceFiber devicesGR740 HW Experience28/11/2019ConsDetailed knowledge of GR740 SOC required, YET:Improved by GRLIB IP reuseDetailed User Manual is providedSome extra Application Notes, e.g. SpW router management, would be helpfulCOMPLEX SPW ROUTER:Extra flexibility induces some extra complexitySuggestions Independent direct SpW link“Easy” bypass mode0005-0011485879
14. GR740 Coding Experience28/11/20190005-0011485879
15. ProsSPARC SUPPORT Zero extra effort to port generic code (ASW like)Ex: LIBPUS from CNES ported smoothlyNATURAL GRLIB code evolutionSmoothen drivers understanding/developmentMinimalize code impact on upper layers.RTEMS 5.1 & RCC BSPReady to use Operating System available under GPLMany code examples providedCover a very large set of configurationsGR740 CODING Experience28/11/2019ConsbootING SW IS HARD TO CODE since:SMP implies CPUs sequencing initialization (master core and slaves cores)Cache managementNumerous IOs management (setup correct init state)May prevent custom BOOT development by end users.RTEMS 5.1 & RCC BSPLack of control guards on SW misbehavior especially in SMPStack management is error-proneMMU usage unavoidable to develop traditional OBSWHypervisor needed or minimalistic equivalentExamples need application notes or extra guidelines to understand how they work and what they do0005-0011485879
16. GR740 DEBUG Experience28/11/20190005-0011485879
17. ProsGRMON3Ready to use and very stableGood level of hardware visibility (info reg cmd)Fast and direct initialization of this complex SoCSPW ROUTER debugging Nice input port tracing feature Instruction and data tracingLegacy instruction and AHB tracing SupportedExtended to 4 CPUEvaluation BOARD:Cover numerous IOs and communication busesClose to a typical designGR740 DEBUG Experience28/11/2019ConsGRMON3:Manual CPU identification for passing command Need to start GDB to perform intensive debugRTEMS 5.1 OS awareness is not yet fully supportedOn-going work at C.G but consolidation of RCC required (RTEMS 5.x kernel still under development)Spacewire router debugging Tracing could be extended by a small trace buffer tracing packet headers.Instruction and data tracingInternal memory limitedHard to understand execution flow without OS awarenessExternal parallel port missing (due to package limitation)Suggestion : introduction of external tracing using SerDes.GRSIM not YET availablePrevent initial code adjustment before going on the real target0005-0011485879
18. Contact Usmaxime.guimard@thalesaleniaspace.comQuestions?28/11/20190005-0011485879