2014-12-11 115K 115 0 0

##### Description

Asynchronous Sequential Logic 81 Chapter 8 Asynchronous Sequential Logic Brief Introduction Introduction An asynchronous sequential circuit is a sequential circuit whose behavior de pends only on the order in wh ID: 22298

**Direct Link:**Link:https://www.docslides.com/marina-yarberry/asynchronous-sequential-logic-585

**Embed code:**

## Download this pdf

DownloadNote - The PPT/PDF document "Asynchronous Sequential Logic Chapter" is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.

## Presentations text content in Asynchronous Sequential Logic Chapter

Page 1

8. Asynchronous Sequential Logic 8-1 Chapter 8. Asynchronous Sequential Logic (Brief Introduction) Introduction An asynchronous sequential circuit is a sequential circuit whose behavior de- pends only on the order in which its input signals change and can be affected at any instant of time. In addition to the FFs, a register may have combinational gates that con- trol when and how new information is transferred into the register. state input output excitation Delay Logic Combinational Figure 1: Asynchronous sequential circuit model. ;x ;:::;x input variables ;z ;:::;z output variables ;y ;:::;y state variables (present state) ;Y ;:::;Y excitation variables (next state) State transition occurs when there is an input change (no clock pulses). Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005

Page 2

8. Asynchronous Sequential Logic 8-2 Memory (delay) elements are either latches (unclocked) or time-delay ele- ments (instead of clocked FFs as in a synchronous sequential circuit). An asynchronous sequential circuit quite often resembles a combinational circuit with feedback. Faster and often cheaper than synchronous ones, but more difﬁcult to design, verify, or test (due to possible timing problems involved in the feedback path). Steady-state condition ;:::;k; )= To ensure proper operation, simultaneous changes of 2 or more input variables are usually prohibited. Fundamental-mode operation : only one input variable can change at any time, and the time between 2 input changes must be longer than the time it takes the circuit to reach a stable state. Analysis Procedure The analysis consists of obtaining a table or a diagram that describes the sequence of internal states and outputs as a function of changes in the input variables. 1. Determine all feedback loops. 2. Designate each feedback-loop output with and its corresponding input with for ;:::;k , where is the number of feedback loops. 3. Derive the boolean functions for all ’s. 4. Plot the transition table from the equations. Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005

Page 3

8. Asynchronous Sequential Logic 8-3 Transition table 10 00 10 11 01 11 01 00 10 11 01 00 ysub ysub Ysub Ysub ysub ysub Excitation variables and Secondary variables and xy xy The delay associated with each feedback loop is obtained from the propaga- tion delay between each input and its corresponding output. In an asynchronous sequential circuit, the internal state can change immedi- ately after a change in the input. Total state : internal state + input value. Flow table : a transition table in which states are named by letter symbols instead of speciﬁc binary values. The ﬂow table also includes the output values of the circuit for each stable state. Primitive ﬂow table : one that has only one stable state in each row. To obtain the circuit described by a ﬂow table, it is necessary to assign to each state a distinct binary value, which converts the ﬂow table into a transition table. Race condition : when 2 or more binary state variables change value in re- sponse to a change in an input variable. Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005

Page 4

8. Asynchronous Sequential Logic 8-4 May cause the state variables to change in an unpredictable manner. Noncritical race : ﬁnal stable state does not depend on the order in which the state variables change. Critical race : ﬁnal stable state depends on the order in which the state vari- ables change. For proper operation, critical races must be avoided. Races may be avoided by making a proper state assignment. Races can be avoided by directing the circuit through intermediate un- stable states with a unique state-variable change. Design Procedure 1. Obtain a primitive ﬂow table. 2. Reduce the ﬂow table. 3. Assign binary state variables to obtain the transition table. 4. Assign output values to the dashes to obtain the output maps. 5. Simplify the excitation and output functions. 6. Draw the logic diagram. We will design a gated latch circuit with 2 inputs, (gate) and (data), and one output, . The binary value at the input is transferred to the output when and only when .When falls to 0, the latch retains the value at the output, which does not change even if changes. The table of total states and the corresponding primitive ﬂow table is shown below. Note that both inputs are not allowed to change simultaneously ( entries in the table). Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005

Page 5

8. Asynchronous Sequential Logic 8-5 states to be merged Primitive Flow Table e; e; d; d; e; b; b; b; b; a; a; a; a; f; f; c; c; c; 10 11 01 00 DG Table of Total States After or After After or Comments Output Inputs State After The next step is to reduce the primitive ﬂow table, which is shown below. Then, b; b; a; a; b; a; b; a; 10 11 01 00 DG e; b; a; f; d; b; a; c; b;e;f a;c;d 10 11 01 00 DG following state assignment, we convert the ﬂow table into a transition table (by assigning and ). From the table, the simpliﬁed O/P function ( )and the excitation function ( ) with respect to ,and can be derived using the K-map method. Note that the don’t-cares are assigned such that DG Y: Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005