Sanghwa Park SNURIKEN PHENIX Run12 510GeV 5 weeks The first PHYSICS run March 18 th The last PHYSICS run April 18 th 20121 20122 20123 20124 PP200GeV PP510GeV MuTRG FEEFrontEndElectronics ID: 780302
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Slide1
Muon Trigger Performance Run12 PP510GeV
Sanghwa Park
(SNU/RIKEN)
Slide2PHENIX Run12 510GeV
5 weeks
The first PHYSICS run: March 18
thThe last PHYSICS run: April 18th
2012/1
2012/2
2012/3
2012/4
PP200GeV
PP510GeV
Slide3MuTRG-FEE(Front-End-Electronics)Momentum sensitive trigger & fast readout electronics
RPC (Resistive plate chamber)
Good timing resolution
Hadron absorberReject hadron(K, π) to muon
decay
Trigger
Upgrade History
2008200920102011
MuTRG
-FEE (North arm)
MuTRG
-FEE (South arm)
RPC3 (North)
RPC3 (South)
Hadron
Absorber
RPC1
Slide4W Trigger System
MuTRG
ADTX
MuTRG
MRG
Level 1
Trigger
BoardMuTrFEE
Resistive Plate Counter
(RPC) (Φ segmented)
B
2 planes
5%
95%
Trigger
Trigger
Trigger
Interaction Region
Rack Room
Optical
1.2Gbps
Amp/Discri.
Transmit
Data
Merge
MuTRG
RPC
FEE
Trigger events with straight track
(e.g.
D
strip <= 1)
RPC / MuTRG data are
also recorded on disk.
Slide5Run12 MuTRG-EFF Parameters
Parameters
Threshold
97% efficiency threshold
-> 95%
efficiency threshold
(changed during run period for higher rejection power)DiscriminatorLEDGap LogicStation1
Station2 and 3AND2ORLL1 width3 BCLK
Slide6MuTRG-FEE Timing Optimization
Limitation of broad timing resolution: ~2-3BCLK
Extend timing window to 3BCLK(maximum)
BCLK Binning in ADTX
Offset
BCLK
Entry (Normalized)
Motivation:
Find
best timing offset which
maximize entries in finite timing window
42.9 nsec
88.3 nsec
6
Slide7Inserted delay fiber cable to MuTrig-FEE GTM line, remaining GTM setting for
MuTr
untouched.Couldn’t adjust timing MuTrigLL1 timing for south arm with fiber delayInsert fiber cable only for north arm, 4m (20 nsec)
MuTRG-FEE Timing Optimization
y-axis:
(3BCLK/Total entries) of st1 * st2 * st3
Slide8New FPGA code uploaded
New FPGA code for
MuTRG
-MRG boards was developed by Katsuro Nakamura.Important changes: - detailed error detection - use independent clock signal for readout
- 10 nsec faster MRG->LL1 output timing
- can give delay to LL1 output timing board by board
New FPGA success story - find suspicious ADTX board id which caused frequent error - solved LL1 efficieny drop problem caused by the above error
Slide9W Trigger Rejection Power
Needed to set
prescale
when luminosity is high
We had kept two w trigger during entire pp510
GeV
run period
Slide10W Trigger Check
Run11 w trigger: SG1xMUIDxBBC(
noVtx
)Run12 w trigger: SG1xRPC3xBBC(noVtx)
Slide11Muon yield
Cut Parameters
DG0 < 5.0
DDG0 < 1.0
Chi2 < 8.0
DCA_r
<3.0DCA_z < 7.0DG4 < 4.8
MUID lastGap == 41.5 <eta < 2.2 for north, -2.2 < eta < -1.5 for south*RpcDCA > 0 was not applied for this result.SG1xMUIDxBBCSG1xRPC3xBBCSG1xMUIDxBBCSG1xRPC3xBBCSouthNorth(* not scaled)Big difference between two trigger, especially in low pT region
Slide1212
Muon
yield
: SG1xRPC3 south
: SG1xMUID south
: SG1xRPC3 north
: SG1xMUID north
Run set2
Slide1313
South SG1xRPC3xBBC
North SG1xRPC3xBBC
South SG1xMUIDxBBC
North SG1xMUIDxBBC
RpcDCA
distribution
(all pT region)Same trigger, South and North comparison In low pT region, SG1xMUID north yield is larger tham south. It seems it corresponds to this region. In other hands, in high pT region, SG1xMUID south yield is larger than north, and this difference is showed in small RpcDCA region.
Slide14Closer look at high pT > 5 GeV
/c region…
RpcDCA
[cm]
RpcDCA
[cm]
SG1xMUIDxBBCSG1xRPC3xBBC
SouthSG1xMUIDxBBCSG1xRPC3xBBCNorthBasically used same cuts with muon yield plots.Additional cut: pT > 5 GeV region only.14
Slide1515
Used same cut parameters as slide4,
bu
t required one more cut additionally.
If
we require RpcDCA
> 0, the difference between SG1xMUIDxBBC south and north is drastically reduced!RpcDCA cut: before/afterRed: before RpcDCA>0 cutBlack: after RpcDCA>0 cutRed: before RpcDCA>0 cutBlack: after RpcDCA>0 cutSG1xRPC3xBBC southOrange: before RpcDCA>0 cutBlack: after RpcDCA>0 cutOrange: before RpcDCA>0 cutBlack: after RpcDCA>0 cutSG1xMUIDxBBC south
Slide16RpcDCA
cut: before/after
16
Used same cut parameters as slide4,
bu
t required one more cut additionally.
If we require RpcDCA > 0, the difference between SG1xMUIDxBBC south and north is drastically reduced!Cyan: before RpcDCA>0 cutBlack: after RpcDCA>0 cutCyan: before RpcDCA>0 cutBlack: after RpcDCA>0 cutSG1xMUIDxBBC northBlue: before RpcDCA>0 cutBlack: after RpcDCA>0 cutBlue: before RpcDCA>0 cutBlack: after RpcDCA>0 cut
SG1xRPC3xBBC north
Slide17Rpctime distribution (all
pT
region)
SG1xMUIDxBBC
SG1xRPC3xBBC
North
SG1xMUIDxBBC
SG1xRPC3xBBCSouthSG1xMUIDxBBCSG1xRPC3xBBCSouthSG1xMUIDxBBCSG1xRPC3xBBCNorth17
Slide18Closer look at high pT > 5 GeV
/c region…
SG1xMUIDxBBC
SG1xRPC3xBBC
South
SG1xMUIDxBBC
SG1xRPC3xBBC
NorthBasically used same cuts with muon yield plots.Additional cut: pT > 5 GeV region only. RpcDCA >0, for rough association with MuTR hit (No difference, between with RpcDCA>0 cut and without RpcDCA>0 cut)18
Slide19In high pT region, two triggers are getting consistent. RpcDCA
>0 cut makes drastic difference.
Based on study, we set
prescale to SG1xMUIDxBBC trigger in high luminosity beam.Working on this for more deeper study: - luminosity correction
Slide20MuTrig LL1 Efficiency
South octant3
South octant5
MuTrig
LL1 was overall stable, and in good state.
BUT, south octant5 was not stable, and the efficiency was low.
-> couldn’t figure out the reason yet.SG1xBBCnoVtx trigger
Slide21MuTrig
LL1 Efficiency
Thanks to the great effort of LL1 experts,
MuTrig
LL1 timing adjustment was successfully done.
SG1xRPC3xBBC trigger was in bad state for one day.
South octant3SG1xRPC3xBBCnoVtx trigger
Slide22MuTRG-FEE Error Monitoring
South
North
Oct8,1
Oct2,3
Oct4,5
Oct6,7
No errorKnown errors. To be fixed during shutdown22ADTX boards have been in good operation status except for known bad boards.
Slide23Summary
We had taken data over 30 pb-1 this year.
Several update:
Fiber insertion to MuTrig-FEE for increasing efficnecyNew FPGA code was successfully uploaded- Figured out bad ADTX boards, and need replace during shut down period
New w trigger was introduced: SG1xRPC3xBBC
MuTrig
LL1: need to figure out south octant5 low efficienyThank you for great effort of all
Slide24Backup
Slide25Integr. Luminosity
Slide26Run11
vs
Run12 GTM scan result
South St1
South St2
South St3
North St3North St2
North St1Delay time [nsec]Delay time [nsec]Delay time [nsec]Delay time [nsec]Delay time [nsec]Delay time [nsec]26Spin PWG meeting February 22, 2012
Slide27Final Result
Optimized delay: 14.2
South
North
Optimized delay: 24.3
y
-axis= st1 * st2 * st3
27Spin PWG meeting February 22, 2012
Slide28MuTRG operation in 2011
Parameters
Average Threshold
25 mV
Discriminator
LED
Gap LogicStation1Station2 and 3AND2
ORLL1 width3 BCLKEfficiency at Plateau92% (South arm)87% (North arm)
Slide29Slide30LL1 Trigger efficiency
LL1 Trigger efficiency?
RPC
St3
St2
St1
MuTRG
-ADTX boardsMuTRG-MRGhit patterncopyLL1 TriggerDCMIF
DCM
Trigger
Real trigger fire
Expected trigger fire
Inequality?
LL1 Efficiency
Slide31MuTrig LL1 Effiency
(SG1xBBC north)
Slide32MuTrig LL1 Effiency
(SG1xBBC south)
South octant5
Xaxis
: Run Number,
Yaxis
: Efficiency
Slide33MuTrig LL1 Effiency
(SG1xRPC3 north)
Slide34MuTrig LL1 Effiency
(SG1xRPC3 south)