1 Role of Standards in TLM - PowerPoint Presentation

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Role of Standards in TLM

driven D&V Methodology

Umesh Sisodia, CircuitSutra

(usisodia@circuitsutra.com)Slide2

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ObjectiveCircuitSutra:

SoC

Modeling Services

Embedded software services using Virtual Platforms

By the end of session you should:Know about various standards in SoC modeling domainRole of standards in TLM D&VHow does CircuitSutra’s expertise in SoC modeling standards fits with the Cadence tools to implement the TLM D&VQ&A session after the presentationPrize draw in the end. You can win a copy of the book ‘TLM driven design and verification methodology’ Slide3

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Modeling StandardsModeling Language: SystemCFull power of C / C++

Structure (module, hierarchy, ports)

Concurrency, Simulation time

Precision: Fixed point and bit accurate data types

Transaction level modeling (TLM)OSCI TLM2.0OSCI TLM1.0Extending TLM2.0Bus specific protocols (AMBA, PLB, .. )Non memory map protocols (UART, USB, Ethernet, .. )STARC TLM GuidelinesSystemC Synthesizable subsetSlide4

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Benefits of StandardsEasy to integrate IP models from different sources

Models are independent of ESL / EDA tool environment

Any verilog code is supposed to work with EDA tool from any vendor

Similarly SystemC models should work with any ESL tool

(Necessary condition for SystemC to become a language of choice for design entry, and hence for raising the abstraction of chip design)Feasible to mix tools and expertise from different vendors in the TLM D&V FlowVirtual platform environment: ARM Fast Model, OVP, ..HLS: Cadence C-to-SVerification: Calypto, Cadence, SystemC Modeling Services (CircuitSutra)Different parts of a model can be sourced from different vendorThe Untimed / Loosely timed model from one vendor can be combined with bus specific transactor from another vendorAllows the Code re-use across different applications / architecturesEasy to get engineering professionals Slide5

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Components of TLM D&V flowCadence is advocating Standards based TLM D&V methodology

Virtual Platform of a

SoC

TLM2.0

wrapper created over fast processor modelPeripheral models created using SystemC & TLM2.0Computation is separate from communication as per STARC TL GuidelinesSynthesizable models for HLSFunctionality implemented using Synthesizable SystemC subsetComputation is separate from communication as per STARC TL GuidelinesTLM Interfaces: TLM1.0 + GP (Borrowed from TLM2.0) = Cadence TLM+GPBus specific Transactors (TLM+GP interface on one end, bus specific signal level interface on other end)

Verification

Verification of TLM Models (TLM2.0, HLS Ready TLM, HLS Ready Signal)

Verification of RTL Blocks

Accelara

UVM

can be effectively used to

verifiy

across abstraction levels

HW / SW

Coverification

through Incisive Software Extensions (ISX)Slide6

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Virtual Platform of SoCAllows the embeded

software development without FPGA board

Chip design and

eSW

can proceed in parallel. Reduces TTM for SoCAdvanced tools are being available for better eSW development and debuggingSlide7

VP Methodology

A typical virtual platform project

TLM2.0 Sockets

tlm_usb Socket

New SystemC models added

Existing components of ARMIntegratorCP platform

Ethernet driver of host PC

USB driver of

host PC

tlm_ethernet Socket

tlm_uart Socket

DecodeBus (m_bus)

ARM CPU

DMA

PIC

IRQ

FIQ

TLM Memory

UART

Uart

backend

Driving the console

Other Slave peripherals of ARM IntegratorCP Platform

USB Backend

USB Controller

Ethernet Backend

Ethernet

Controller

ARMIntegratorCP

Board

Virtual Platform

Environment

ARM

Fast

Models, OVP, QEMU, ..

Any other vendor ..Slide8

Models for Virtual Platforms

Traffic Generator

Ethernet

Controller

TLM 2.0

Model

Backend

TLM-Ethernet

Extends TLM2.0

Virtual Network

Ethernet

Controller

Ethernet

Controller

Backend

Ethernet Driver

(Host PC)Slide9

Accessing host interfaces in VP

Ethernet

Controller

TLM 2.0

TLM-Ethernet

Extends TLM2.0

Backend

Ethernet Driver

(Host PC)

TLM 2.0

TLM-USB

Extends TLM2.0

USB Host

Controller

Backend

USB Driver

(Host PC)

VP

Guest OS

Device Driver

Application

Guest OS

Android /

Symbian

Device Driver

Application

Host OS

Host OS

Windows 7 /

Linux

Enables the virtual platform to interface with real world devices

Provides real time verification environment

Any hardware interface of host PC can be supported

Ethernet

WLAN

USB

Printer

Camera

Audio(Speaker,

Mic

)

..Slide10

Model Architecture

Wrapper

Wrapper

Core

(Functional model)CommunicationCycle Accurate ModelNon blocking interface (AT)

TLM2.0 extended for Bus specific protocol

TLM2.0 Compliant Model

Blocking Interface (LT / UT)

Non blocking interface (AT)

TLM2.0 Socket

Adaptor (PV – CA)

CA TLM Socket

Pin level interface

Adaptor (PV – BS)

Bus Signal Interface

Can connect to the RTL

Pin interface is specific to a bus

Pin level interface

Adaptor (PV – BS)

AXI

Pin level interface

Adaptor (PV – BS)

PLB

Pin level interface

Adaptor (PV – BS)

OCP

STARC TL Guidelines: Computation is separate from communicationSlide11

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High Level Synthesis

HLS Tool

C-to-Silicon Compiler

RTL (Verilog)

TLM modelSystemC, C, C++SystemC: Language of Design entryDesigners focus on implementing the functionality

HLS Tool: Generate optimized RTL

RTL

Power

RTL

Area

RTL

Performance

Optimized For:

Constraints

Constraints

RTL

90 nm

RTL

45 nm

RTL

22 nm

Optimized For:

Process Node

RTL

FPGA

Altera

RTL

FPGA

Xilinx

RTL

ASIC

Optimized For:

Underlying Fabric

Optimized For:

Bus Architecture

RTL

AXI

RTL

PLB

RTL

OCP

TLM-GP Interfaces

Transactors

Benefits

Only one version of design

Less amount of code

Fewer bugs

Function is seperated from implementation

Raises the abstraction of Chip Design

SystemC may replace Verilog

CircuitSutra have good expertise in Synthesizable SystemC subsetSlide12

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Models for VP & HLS

Virtual Platform

HLS

Simulation Speed

Can use all the constructs of SystemCTLM2.0 for bus interfacesTLM interfaces for non memory mapped connectionsSynthesizabilityOnly Synthesizable subset of SystemC should be usedTLM1.0, TLM+GP (Cadence)Pin level interfaces for non memory mapped connectionsSlide13

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Models for VP & HLS

Virtual Platform

HLS

Core

(SystemC)Communication(TLM2.0)

Core

(Synthesizable SystemC)

Communication

TLM+GP

HLS Ready TLM

TRANSACTOR

HLS Ready Signal

TLM-UART

Sout

Sin

ModemSlide14

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Verification from TLM to RTL New verification methodology required for new design methodology

Effortlessly reuse verification IP from TLM to RTL closure

The proven RTL verification concepts (UVM, MDV etc.. ) can be used

The UVC can be extended to verify

SystemC based TLM designs Complete System (HW & SW)Incisive Software extensions (ISX) enables the verification environment to connect to software using Generic Software adaptor (GSA) Reduce the verification effortsThe functionality of the computation block should be verified at the highest abstraction level Fewer bugsFaster simulationEasier to identify, understand and fix the bugsThe interfaces, protocol correctness can be verified at HLS ready levelDetailed timing can be verified at RTL levelSlide15

HW/SW Co-Verification

Hardware

Software

SoC (VP)BUS UVC

Peripheral UVC

Peripheral UVC

Automatic System scenario generator

UVM Infrastructure

Software UVC

ISX

Incisive Software Extensions (ISX)

Extends system verification environment to include software

MDV can be applied to verify the low level hardware dependent software

CircuitSutra can integrate the VP with ISXSlide16

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Standardization required ..TLM modeling standard for non memory mapped communication protocolUSB

Ethernet

WLAN

Zigbee

..Standard definition of abstraction levels for different use casesPV, AV, VVOCP-IP: TL4, TL3, TL2, TL1STARC TL Guidelines: Slide17

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System Realization Alliance

Advocating Standards based TLM D&V methodology

Standards based SoC modeling services

Can help mutual customers to quickly get started with TLM D&VSlide18

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CircuitSutra OfferingsCreate virtual platform of System on Chip (SoC)

Integrate the Virtual platform with Cadence ISX

Synthesizable models for High Level Synthesis (HLS)

Create models as per SystemC Synthesizable subset

Synthesize using C-to-Silicon compilerSystemC models for RTL verification or HW / SW coverificationBus specific Adaptors / TransactorsOCP-IPAMBA Kit Embedded software services using virtual platformsSlide19

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