Module 3.C Serial Peripheral Interface (SPI) PowerPoint Presentation, PPT

Module 3.C Serial Peripheral Interface (SPI) PowerPoint Presentation, PPT - DocSlides

Tim Rogers 2017. Learning Outcome #3. “. An ability to effectively utilize the wide variety of peripherals integrated into a contemporary microcontroller. ”. How?. A. : . Clocks and Real . Time Interrupt (RTI). ID: 720043

By mitsue-stanley
Watch All docs

Likes : 2
Views : 5

Download this presentation

Click below link (As may be) to get this presentation.

Module 3.C Serial Peripheral Interface (SPI)

Download Note - The PPT/PDF document "Module 3.C Serial Peripheral Interface (..." is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.

Presentations text content in Module 3.C Serial Peripheral Interface (SPI)

Module 3.C
Serial Peripheral Interface (SPI)
Tim Rogers 2017
Slide2
Learning Outcome #3
“
An ability to effectively utilize the wide variety of peripherals integrated into a contemporary microcontroller
”
How?
A
: Clocks and Real Time Interrupt (RTI)B: Analog-to-Digital Converter (ATD)C: Serial Peripheral Interface (SPI)D: Timer Module (TIM)E: Pulse Width Modulation (PWM)F: Serial Communications Interface (SCI)
[
3.B
]-2
Slide3
Learning Outcome #3
“Serial Peripheral Interface (SPI)”
Why?
[
3.B
]-
3Want to communicate with a peripheral
Better option:
Send multi-bit data serially
One options:
Send data in parallel
CLK
Data
Slide4
Basic Description
Communication takes place seriallySynchronous because a clock signal is involved
Operates in Master/Slave Mode.
Needs to be at least one master – can be multiple slaves
Master defines the clockOperates via “shifting in” bits each clock cycle[3.B]-4
Standardized and used for a variety of peripherals: LCDs, D/A converters, etc…
Can also use it to communicate between microcontrollers
Slide5
Basic SPI Operation
[3.B]-
5
MOSI
– Master Out, Slave In
MISO
– Master In, Slave Out
MASTER
SLAVE
Master owns the clock
Slide6
9S12 SPI Module
Full-DuplexCan manipulate SPI clock
Can be program or interrupt-driven.
https://
engineering.purdue.edu/ece362/Refs/9S12C_Refs/S12SPIV3.pdf[3.B]-
6
Slide7
SPI Block Diagram
Port M
24 MHz
PM.2
PM.4
PM.3
PM.5
7
Slide8
SPI Registers
SPICR1 (SPI control register 1)
SPIE (bit 7)
“0” –
SPI interrupts disabled
“1” – SPI interrupts enabled
SPE (bit 6)“0” – SPI system disabled“1” – SPI system enabled
SPTIE (bit 5)
“0” – SPTEF (transmit empty) interrupt disabled
“1” – SPTEF
(transmit empty)
interrupt enabled
indicates default mode after RESET
8
Slide9
SPI Registers
SPICR1 (SPI control register 1)
MSTR (bit 4)
“0” –
slave mode enabled
“1” – master mode enabled
CPOL (bit 3) “0” – active high clock (SCK low in idle state)
“1” – active low clock (SCK high in idle state)
CPHA (bit 2)
“0” – data sampling occurs at odd edges of SCK
“1” –
data sampling occurs at even edges of SCK
indicates default mode after RESET
9
Slide10
SPI Clock Format with CPOL=0, CPHA=0
10
Slide11
SPI Registers
SPICR1 (SPI control register 1)
SSOE (bit 1)
“
0” –
slave select output disabled
“1” – slave select output enabled (in master mode, provided MODFEN bit is also “1”)LSBFE (bit 0) “0” – data transferred most significant bit first
“1” – data transferred least significant bit first
indicates default mode after RESET
11
Slide12
SPI Registers
SPICR2 (SPI control register 2)
BIDIROE
(bit 3) – MOSI/MISO output enable in bi-directional mode
“
0” –
output buffer disabled“1” – output buffer enabledSPC0 (bit 0) – serial pin control bit
“
0” – bi-directional mode is disabled
“1” – bi-directional mode enabled
indicates default mode after RESET
12
Slide13
SPI Modes
Key
:
M
aster
S
lave Input Output
Master
13
Slide14
SPI Registers
SPIBR (baud rate)
SPRx (bits 2-0) – baud rate pre-selection bits
SPPRx (bits 6-4) – baud rate selection bits
BaudRateDivisor = (SPPR + 1)
 2
(SPR + 1)BaudRate = BusClock / BaudRateDivisor
Example: If SPR=
000 and SPPR=
000
(default),
then BaudRateDivisor = 2 
BaudRate = BusClock/2
14
Slide15
SPI Registers
SPISR (status)
SPIF (bit 7) – set after a received data byte is copied into the SPI data register
“0” –
transfer not yet complete
“1” – received data copied to SPIDR
SPTEF (bit 5) – set when the transmit data register is empty“0” –
SPI transmit data register not empty
“1” – SPI transmit data register is empty
indicates default mode after RESET
Cleared
by reading SPISR (status) register followed by reading SPIDR (data) register
15
Slide16
SPI Registers
SPIDR (data register)
serves as both the input and the output data register for the SPI
PORTM (Port M data register)
MISO (bit 2)
SS (bit 3)
MOSI (bit 4)SCK (bit 5) 16
Slide17
The “synchronous” aspect of an SPI interface means:
data can only be transmitted in one direction
data can be transmitted in both directions, but not at the same time
data can be transmitted in both directions simultaneously
data transmission requires a clock signal
none of the above
17
Slide18
The
minimum
SPI baud rate divisor possible is:
1
24
8
none of the above18
Slide19
Based on a 24 MHz system clock, the
maximum
SPI data transfer rate possible (in bits/second) is:
2,000,000 bps
4,000,000 bps
8,000,000 bps12,000,000 bps
none of the above19
Slide20
The
maximum
SPI baud rate divisor possible is:
128
8962048
4608
none of the above20
Slide21
Based on a 24 MHz system clock, the
minimum
SPI data transfer rate possible (in bits/second) is approximately:
8,000 bps
11,719 bps
93,750 bps1,500,000 bps
none of the above21
Slide22
SPI Initialization Code
[3.B
]-
22
; Select 1.5 Mbps baud rate (24 MHz bus
)
spini
movb
#$
12,spibr
Slide23
SPI Registers
SPIBR (baud rate)
SPRx (bits 2-0) – baud rate pre-selection bits
= 010
SPPRx (bits(6-4) – baud rate selection bits
= 001
BaudRateDivisior = (1 + 1)  2 (2
+ 1)
= 16
BaudRate = 24 MHz / 16 = 1.5 Mbps
SPIBR = x 001 x 010 = $12
23
Slide24
SPI Initialization Code
[3.B
]-
24
; Select 1.5 Mbps baud rate (24 MHz bus
)
spini
movb
#$12,spibr
; Master mode, Interrupts off, CPOL=0,
; CPHA=0, slave select disabled, data
; transferred most significant bit first
movb
#$
50,spicr1
Slide25
SPI Registers
SPICR1 (SPI control register 1)
SPIE (bit 7)
“0” –
SPI interrupts disabled
“1” – SPI interrupts enabled
SPE (bit 6)“0” – SPI system disabled
“1” – SPI system enabled
SPTIE (bit 5)“0” –
SPTEF interrupt disabled
“1” – SPTEF interrupt enabled
indicates default mode after RESET
25
Slide26
SPI Registers
SPICR1 (SPI control register 1)
MSTR (bit 4)
“0” –
slave mode enabled
“1” – master mode enabled
CPOL (bit 3) “0” – active high clock (SCK low in idle state)
“1” – active low clock (SCK high in idle state)
CPHA (bit 2)
“0” – data sampling occurs at odd edges of SCK
“1” –
data sampling occurs at even edges of SCK
indicates default mode after RESET
26
Slide27
SPI Registers
SPICR1 (SPI control register 1)
SSOE (bit 1)
“
0” –
slave select output disabled
“1” – slave select output enabled (in master mode, provided MODFEN bit is also “1”)LSBFE (bit 0) “0” – data transferred most significant bit first
“1” – data transferred least significant bit first
indicates default mode after RESET
27
Slide28
SPI Initialization Code
[3.B
]-
28
; Select 1.5 Mbps baud rate (24 MHz bus
)
spini
movb
#$12,spibr
; Master mode, Interrupts off, CPOL=0,
; CPHA=0, slave select disabled, data
; transferred most significant bit first
movb
#$
50,spicr1
; Normal (non-bidirectional) mode
clr
spicr2
rts
Slide29
SPI Registers
SPICR2 (SPI control register 2)
BIDIROE
(bit 3) – MOSI/MISO output enable in bi-directional mode
“
0” –
output buffer disabled“1” – output buffer enabledSPC0 (bit 0) – serial pin control bit
“
0” – bi-directional mode is disabled
“1” – bi-directional mode enabled
indicates default mode after RESET
29
Slide30
SPI transmit/receive code
[3.B]-
30
;Transmit data passed in A register
;Return data read in B register
;Transmit - wait for SPTEF to set
spio
brclr
spisr,$20,spio
staa
spidr
;transmit data
;Receive - wait for SPIF to set
sprlp
brclr
spisr,$80,sprlp
ldab
spidr
;read data
rts
Slide31
SPI Registers
SPISR (status)
SPIF (bit 7) – set after a received data byte is copied into the SPI data register
“0” –
transfer not yet complete
“1” – received data copied to SPIDR
SPTEF (bit 5) – set when the transmit data register is empty“0” –
SPI transmit data register not empty
“1” – SPI transmit data register is empty
indicates default mode after RESET
Cleared
by reading SPISR (status) register followed by reading SPIDR (data) register
31
Slide32
SPI Application – Multiple I/O Devices
32
Slide33
SPI Application
– 8-bit Shift
Register/ Constant Current LED Driver
33
MOSI
SCLK
GPIO
GPIO
MISO (optional)
Slide34
SPI Application –
External 12-bit ATD
34
Slide35
SPI Application –
External 8/10/12-bit DTA
35
Slide36