So 14 bits 50MHz would be fast enough Real time processing up to 30kHz count rate energy only Data rate 30k x energy 2 timestamp 6 ID 2 300kBytessecond per channel 12Mbytessec4 chan card 100 channels 30Mbytessec brPage 2br Ian Lazarus Nuclea ID: 23764
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Nuclear Physics Group•Nicely packaged for our application•Volume users (Radar, software radio)= sensible price•Powerful FPGA built in-DSPs too.•Can process 50kHz singles rate on 48 channels•160/320Mbytes/sec (diagnostic). Normally 20Mbytes/sec output.•Needs interface card for TDR port and analogue matching Nuclear Physics Group Gestrip detector (12 x 12) digitiser withFPGA �30k slices digitiser withFPGA �30k slices digitiser with digitiser with Processing. Time-order and merge.Gestrip detector (12 x 12) 4x PC 20 or 320 Mbytes/secto PC over Gbitor 10Gbit etherOr other fast links Necessary, but not shown:1)Timestamp system tostamp all data when CFD fires.2)Common ADC clock3)Sync for timestamps4)Reset and Error timestamp5)Control/setup bus/net Tender includes all parts Gestrip detector (12 x 12) digitiser withFPGA �30k slices digitiser withFPGA �30k slices digitiser with digitiser with Processing. Time-order and merge.Gestrip detector (12 x 12) 4x PC 20 or 320 Mbytes/secto PC over Gbitor 10Gbit etherOr other fast links Necessary, but not shown:1)Timestamp system tostamp all data when CFD fires.2)Common ADC clock3)Sync for timestamps4)Reset and Error timestamp5)Control/setup bus/net Tender includes all parts Nuclear Physics Group 12 12 12 12 Clk trig gpio Clk Exttrig gpio Clk Exttrig gpio Clk Ext gpio ADCs ADCs ADCs ADCs FPGA FPGA FPGA FPGA FPDP CPCI FPDP CPCI FPDP CPCI FPDP CPCI CPCI for setup, control, readout CPCIhost FPDP1 CPCI FPDP1 FPDP1 FPDP1 Reconstruction PC (with 2 PCI-FPDP Interfaces from Conduant) PCI -FPDP PCI -FPDP FPGA FPGA FPDP1 CPCI FPDP1 FPDP1 FPDP1 FPGA FPGA First Configuration : Diagnostic Mode (Multi-Channel, Phase-Synchronous Data Recording) QuadSignal-Quad 80MB/s160MB/s RAID RAID Max BW :FPGA-FPGA = 100MB/secFPDP1 = 200MB/sec Nuclear Physics Group For CCLRC DaresburyUKP05-2378 Rev xaAugust 25, 2005Unit B (12 ADC Group) 4-ch ADC+ 3-m gate FPGA: PMC data Control 4-ch ADC+ 3-m gate FPGA: PMC data Control1.5m gate 4-ch ADC+ 3-m gate FPGA: PMC data Control 1.5m gateFPGA Card B1: PCI Carrier with PMC slotsCard B2: PCI Carrier with PMC slots To Unit C(160 Mbytes/sec)Data: B2 From Unit A(80 Mbytes/sec)Unit B is very similar to Unit ACard B2 accepts the output of Unit A merges the data with the data from the PMC in Card B2 & sends it to card Nuclear Physics Group75MHz, 14-bit digitizing of input signalSimultaneous amplitude measurement and PSAPulse heights measured with up to 15 bits accuracy Waveform acquisition up to 13.7us for each Programmable gain, input offset, trigger and energy filter parametersTriggers, run synchronization and clocks distributed over PXI backplaneCompared to DGF-4C: A quarter of the size, Up to 13 slots per crate (using 12 = 48 channels).