Author Marc DavisMarsh Last Edited by Richard Garvey 51612 1 Table of Contents 2 EMI on TV Picture EMI Nonisolated Isolated Snubbers Component Selection 3 2011 National Semiconductor Corporation ID: 601932
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Slide1
Switching Power Supply Design: EMI Reduction
Author: Marc Davis-MarshLast Edited by Richard Garvey, 5/16/12
1Slide2
Table of Contents
2
EMI on TV Picture
EMI
Non-isolated
Isolated
Snubbers
Component
SelectionSlide3
3
© 2011 National Semiconductor Corporation.
Introduction – EMI Overview
AGENDA
Noise Sources Identification
Minimize EMI Generation by Layout
Protect Sensitive Circuits From Noise
Conducted EMI and EMI Filters
Snubbers
and Components
Summary
Slide4
4
Introduction – EMI Overview
AGENDA
Noise Sources Identification
Minimize
Noise
Generation
by
Layout
Protect
Sensitive Circuits
from
Noise
Conducted EMI and EMI Filters
Snubbers
and Components
Summary
Slide5
What is EMI & EMC?
5Slide6
6
EMI/EMC Standards
EMC Standards vary by…
Region
US = FCC
Europe = CISPR = EN
Application usageConsumer
MedicalAutomotiveWhat standards do we useFCC part 15 BCISPR 22 = EN 55022Slide7
EMI
/EMC Standards Organizations
United States
Electrostatic Discharge Association (ESD)
Federal Communication Commission (FCC)
Institute of Electrical and Electronic Engineers (IEEE)
Institute of Interconnecting and Packaging Electronic Circuits (IPC)
National Institute of Standards and Technology (NIST)
International Society for Measurement and Control (ISA)
National Standards System Network (NSSN)Society of Automotive Engineers (SAE) International
Telecommunication Industry Association (TIA)Underwriters Laboratories, Inc (UL)US Standard Developing Organizations (ANSI)
International
European Committee for
Electrotechnical
Standardization (CENELEC)
European Telecommunications Standards (ETSI)
Institute of Electrical and Electronic Engineers (IEEE)
International
Electrotechnical
Commission (IEC)
International Organization for Standardization (ISO)
International Special Committee on Radio Interference (CISPR)
International Telecommunication Union (ITU)
7Slide8
Links
EU
EMC Directives:
http://ec.europa.eu/enterprise/sectors/electrical/documents/emc/legislation/index_en.htm
EU
EMC Standards List (24 Feb 2011
):
http
://eur-lex.europa.eu/LexUriServ/LexUriServ.do?uri=OJ:C:2011:059:0001:0019:EN:PDFFCC Rules (Title 47 Telecommunications, Part 2):
http://www.access.gpo.gov/nara/cfr/waisidx_10/47cfr2_10.htmlFCC Rules (Title 47 Telecommunications, Part 15) Information Technology Equipment (ITE)
:http://www.access.gpo.gov/nara/cfr/waisidx_10/47cfr15_10.htmlFCC
Rules (Title 47 Telecommunications, Part 18)
Industrial, Scientific, & Medical Equipment (ISM)
:
http://www.access.gpo.gov/nara/cfr/waisidx_10/47cfr18_10.html
FDA
Inspection and Compliance (Medical devices are exempt from FCC regulations):
http://
www.fda.gov/ICECI/Inspections/InspectionGuides/ucm090621.htm
8Slide9
9
Conducted vs. Radiated Emission Limits
Conducted
Radiated
FCC/CISPR Conducted Emission Limits
FCC and CISPR standards somewhat different
FCC B (consumer) much more stringent than FCC A (commercial, industrial, and business)
FCC and CISPR standards the same
FCC/CISPR Radiated Emission Limits
Measured at 10mSlide10
10
How Does Noise Show Up in the System?
NOISE SOURCE
Emissions
SUSCEPTIBLE SYSTEM
Immunity
ENERGY COUPLING MECHANISM
Conducted
Electric Fields
Magnetic Fields
Radiated
Low Frequency
Low, Mid Frequency, LC Resonance
High FrequencySlide11
11
Engineering Approach To Mitigate EMI
SUSCEPTIBLE SYSTEM
NOISE SOURCE
Unwanted Emissions
ENERGY COUPLING MECHANISM
Conducted
Electric Fields
Magnetic Fields
Radiated
Identify Significant EMI Sources
Figure Out EMI Coupling Paths
Engineer Circuit Layout To Mitigate EMI
EMI Filters
EMI Filters
Shielding
Shielding
Add EMI Filter /
Snubber
/ ShieldingSlide12
12
SMPSs Are Big Generators Of Radiated And Conducted Emissions
Due to
High power
High
di
/dt on the switches and diodesFast transients (voltage and current)
Not generally enclosed (not shielded)Parasitic inductance and capacitance in current paths
Switch Mode Power Supply
Supply
LOAD
Causing
Noise Conducted to Supply and / or Load
Interfere with circuits in the same system
Interfere with
other
systemsSlide13
Electrically Small Loop Antennas
Electro Magnetic Field Energy is *:
f
: frequency of interest (Hz)
A: loop area of the current path (meters squared)
I
: Current magnitude at the frequency of interest (A)R is measured distance between source and receiver (meters)
13
*Henry Ott’s classic Noise Reduction Techniques in Electronic SystemsSlide14
14
Any
Current must
go from a source of energy and they must
RETURN
to the same source
Theory Behind EMI Mitigation by PCB Layout
Self Inductance
Voltage Spike
Reduce loop area reduces L
B fields cancel each other if current return path is close to current path
14Slide15
15
Which PATH current is going to take?
Current Takes the Path of
Least IMPEDANCE
, NOT the Path of Least RESISTANCE!
Z = R +
jX
High freq components contained by high
di/dt
current can go through different path than their low freq counterpartThus, the loop area enclosed by high freq components can be completely different
Theory Behind EMI Mitigation by PCB Layout
DC Current Path
HF Current PathSlide16
Theory Behind EMI Mitigation by PCB Layout
ElectroMagnetic Field Energy is Proportional To*:
f
2
: frequency of the harmonic of interest
From switching frequency and di/dtA: loop area of the current path
If: current magnitude at the frequency of interest1/r: measured distance r
16
*Henry Ott’s classic Noise Reduction Techniques in Electronic Systems
Reduce Noise Generation
Reduce fsw and high freq component in di
/
dt
Reduce high freq loop areaSlide17
Steps To Mitigate EMI In PCB
Switching components generate high di/dt current
where is the return path?
17
Loop Contains high
di
/
dt
current is CRITICAL PATH.
Slow down switching action
Reduce high freq path enclosed area Slide18
18
EMI Mitigation
Choice of Switching Frequency
Not just for efficiency/space trade-offs
Beware of EMI “keep out” zones
Automotive = 500kHz < AM Band > 2MHz
ADSL = >1.24MHz to avoid channel interference
Harmonics
Choose switching frequency that keeps beat frequency and harmonics out of the EMI range
Spread-Spectrum Switching
LM5088 dithers frequency
and shows up to 20dB
decrease in EMI
Fundamental switching frequency spike reduction and sidebands using spread spectrum switching in the LM5088
Slide19
19
AGENDA
Noise Sources Identification
EMI Overview – definition and standards
Minimize
EMI
Generation
by
Layout
Protect
Sensitive Circuits
from
Noise
Conducted EMI and EMI Filters
Snubbers
and Components
Summary
Slide20
20
Identify Critical Path
Buck Converter
Boost Converter
Buck-Boost Converter
Critical path
Switching Current exist in the input sideSlide21
21
Identify Critical Path
Buck Converter
Boost Converter
Buck-Boost Converter
Critical pathSlide22
22
Identify Critical Path
Buck Converter
Boost Converter
Buck-Boost Converter
Critical path
Non-Inverting
InvertingSlide23
What Can We Do In PCB Layout?
--Buck example
Buck Converter
Boost Converter
Buck-Boost Converter
Minimize critical path area
Separate noisy ground path from quiet ground
23Slide24
24
Buck Converter
Boost Converter
Buck-Boost Converter
Non-Inverting
What Can We Do In PCB Layout?
--Buck-Boost example
-
+Slide25
25
25
Identify Critical Paths In Isolated Converters
Flyback
Converter
Forward Converter
Critical paths
Push-Pull Converter
Half Bridge Converter
Full Bridge ConverterSlide26
26
26
Identify Critical Paths In Isolated Converters
Flyback
Converter
Forward Converter
Critical paths
Push-Pull Converter
Half Bridge Converter
Full Bridge ConverterSlide27
27
27
Identify Critical Paths In Isolated Converters
Flyback
Converter
Forward Converter
Critical paths
Push-Pull Converter
Half Bridge Converter
Full Bridge ConverterSlide28
28
28
Identify Critical Paths In Isolated Converters
Flyback
Converter
Forward Converter
Critical paths
Push-Pull Converter
Half Bridge Converter
Full Bridge ConverterSlide29
29
29
Identify Critical Paths In Isolated Converters
Flyback
Converter
Forward Converter
Critical paths
Push-Pull Converter
Half Bridge Converter
Full Bridge ConverterSlide30
30
AGENDA
Minimize
EMI
Generation
by
Layout
EMI Overview – definition and standards
Noise Sources Identification
Protect
Sensitive Circuits
from
Noise
EMI Filters
Snubbers
and Components
Summary
Slide31
EMI Mitigation by PCB Layout
BUCK Example
Bypass Caps in High
di
/
dt
loop should be placed as close as possible to the switching components
Low side FET SOURCE should be connected as close as possible to the input capacitorApply to critical paths in other SMPS topologies
31
Critical Path Area Reduction
Grounding
High
di
/
dt
Caps
SW Node
FETs & DriverSlide32
32
Lower EMI can be achieved by…
Place capacitors on
same side of board
as component being
decoupled
Locate as close to
pin as possible
Keep trace
width thick and minimized
Connecting to decoupling capacitors
Connecting to output capacitorsSlide33
33
Customer Layout Example
BUCK controller Input Cap GND connection
Input Cap GND
LS FET GND
Input Cap GND
LS FET GND
LS FET GND
Input Cap GND
Customer Board
Eval
BoardSlide34
EMI Mitigation by PCB Layout
Buck Regulator Comparison with Cin location (single Cin, smaller loop area)
34
Critical Path
Area
Reduction
Grounding
High
di
/
dt
Caps
SW Node
FETs & Driver
VIN
VOUT
SW 14.5V max
VOUT 47mVpp
41dBµV/m
34Slide35
EMI Mitigation by PCB Layout
Buck Regulator comparison with Cin location (single Cin, 2.5 times larger area)
35
Critical Path
Area
Reduction
Grounding
High
di
/
dt
Caps
SW Node
FETs & Driver
SW 18.1V max
VOUT 75mVpp
44dBµV/m
Comparison
SW
max
(
V)
Vout
p2p (mV)
EMI
peak (
dBµV
/m)
Smaller Area
14.5
47
41
Larger
Area
18.1
75
44
35Slide36
EMI Mitigation by PCB Layout
Swings from V
IN
or V
OUT
to ground at fsw. Very high dv
/dt node! Electrostatic radiatorRequires a contradiction: As large as possible for current handling and thermal performance,
yet as small as possible for electrical noise reasonsSolutions:Keep inductor very close to FETs, sw-node short & wide
Minimum Copper Width Requirement:36
Critical Path
Area Reduction
Grounding
High
di
/
dt
Caps
SW Node
FETs & Driver
Where T = Trace width in mils, A is current in Amps, and CuWt is copper weight in Ounces. Formula works over a range of 1A to 20A.
Or roughly 30mils per amp for 1 Oz Cu and 60 mils per amp for ½ Oz CuSlide37
EMI Mitigation by PCB Layout
Minimize loop area enclosed by high-side FETs, low-side FETs, and bypass caps
Connect the low-side FET’s source to the input- cap ground directly on the same layer, then connect to the ground plane
Use copper pours for drain and source connections to power FETs
Minimize stray inductance in the power path
37
Critical Path
Area
Reduction
Grounding
High
di
/
dt
Caps
SW Node
FETs & DriverSlide38
EMI Mitigation by PCB Layout
Gate drives are also high
di
/
dt
paths, lower current levelPlace drivers close to MOSFETsKeep C
BOOT and VDD bypass caps very close to driver and FETsMinimize loop area between gate drive and its return path: from source of FET to bypass cap ground
Minimize stray inductance in the power pathAvoid vias in di/dt
pathUse short trace and width > 20mil for CBOOT, CVDD-bypass, and Gate drive
38
Critical Path Area
Reduction
Grounding
High
di
/
dt
Caps
SW Node
FETs & DriverSlide39
R
esistor
in Series w/ Gate
to Slow Down both Rising and Falling Rates; Diode to Reduce Falling Time
EMI Mitigation by PCB Layout
Contradiction on SW node transition rate:
Faster Rising and Falling Times
= Less sw losses = higher EMI generated
Options to Slow Down Rise / Fall TimeUse gate resistor to soften gate ringingKeep between 1 to 10ohms
Low capacitance schottky diode to improve turn off time39
Critical Path Loop Reduction
Grounding
High
di
/
dt
Caps
SW Node
FETs & Driver
Resistor in Series with
Cboot
to Slow Down HS FET Rising RateSlide40
EMI Mitigation by PCB Layout
Ground Plane
Return Current Takes The Least
IMPEDANCE
Path
Unbroken Ground Plane Provides Shortest Return Path – Image current return path
40
Critical Path Loop Reduction
Grounding
Current flow in top layer trace
Ground Plane
Return current path in unbroken ground plane directly under path
Area minimized
B field minimized
Trace or Cut on the ground plane
Ground Plane
Return current path enclose much larger area if the direct path is blockedSlide41
EMI Mitigation by PCB Layout
Ground Shielding Example – Two Layer Board
41
Critical Path
Area
Reduction
Grounding
SW 15.7V max
VOUT 30mVpp
32.5dB
μ
V/mSlide42
EMI Mitigation by PCB Layout
Ground Shielding Example – Four Layer Board w/ Identical Layout / BOM – Two GND Planes in between
42
Critical Path
Area
Reduction
Grounding
SW 13V max
VOUT 23mVpp
27.5dB
μ
V/m
Comparison
SW max
(V)
Vout
p2p
(mV)
EMI
peak (
dBµV
/m)
Two Layer
15.7
30
32.5
Four
Layer
13.0
23
27.5Slide43
EMI Mitigation by PCB Layout
Ground Shielding Example – Four Layer Board w/ Identical Layout / BOM –
w/ CUT under SW node
43
Critical Path
Area
Reduction
Grounding
SW 15.7V max
VOUT 26mVpp
32.5dB
μ
V/m
Comparison
SW max
(V)
Vout
p2p
(mV)
EMI
peak (
dBµV
/m)
Two Layer
15.7
30
32.5
Four
Layer
13.0
23
27.5
Four
Layer w/ GND cut
15.7
26
32.5Slide44
EMI Mitigation by PCB Layout
Ground Plane
Unbroken Ground Plane provides shortest return path to reduce EMI and Best Shielding
Don’t cut ground plane
Keep high power, high
di
/dt current away from ground plane, run separate paths on the top layer to contain itGround plane is for DC distribution and signal reference only, ideally, there should be no current flow on ground plane
Bypass to ground pins, not the plane
44
Critical Path Area
Reduction
GroundingSlide45
45
Switcher Power Modules
(LMZ23610)
CISPR 22 Measurements
10 Amp Current Sharing Eval board
2.8 mm
15 mm
5.9
mm
15 mm
Ease of Use
Webench, Easy to mount & rework
Internal Comp
Built in Vin Capacitors to solve EMI issue, & shielded inductor Slide46
Nano Module – LMZ10501/0 (1A/650mA)
Extremely Small Solution Size
Place on front-side or back-side of PCB
LLP-8 Footprint
Excellent Performance
Low output voltage ripple
High efficiency
Fast transient response
Mounted on PCB
Expanded View
Low EMI
2.5 mm
1.2
mm
3 mm
Complies with CISPR22 Class B Standard
C
OUT
= 10uF
Vout = 1.8V
46Slide47
Innovative Packaging
Key Features:LLP Footprint
Micro SMD is a standard National package running in high volume
Moisture sensitivity level 3
Standard soldering process
Reliability testing on complete module according to NSC standards
RoHS compliance to IPC 1752
1.2
mm
3 mm
2.5 mm
Top View
Side View
Solder Reflow Profile
47Slide48
Passing CISPR22 Class B Radiated EMI
The evaluation board with the default components complies with the CISPR 22 Class B radiated emissions standard.
5Vin, 1.8Vout, 1A load
10uF input capacitor
10uF output capacitor
1nF VCON capacitor
48Slide49
Nano Module - Cispr 25 Class 5 EMI (Radiated)
49
49Slide50
Passing CISPR 25 Class 5 Radiated EMI
Adding two small 0.1μF 0805 input capacitors results in CISPR 25 Class 5 radiated emissions standard compliance
50Slide51
51
AGENDA
Protect
Sensitive Circuits
from
Noise
EMI Overview – definition and standards
Noise Sources Identification
Minimize
EMI
Generation
by
Layout
Conducted EMI and EMI Filters
Snubbers
and Components
Summary
Slide52
Protect EMI Sensitive Nodes from Noise
52
Vout
sensing path and feedback node
Compensation network
Current sensing path
Frequency setting
Monitoring and Protecting Circuits
… …
Sensitive Nodes:
Control and Sensing Circuits
SW node
Inductor
High
di
/
dt
bypass caps
MOSFETs
Power Diodes
… …
Noisy Nodes:
Any Nodes in High
di
/
dt
Loop
Shielded by Ground / Power Planes
Away from EMI sourceSlide53
Good Practice to Protect EMI Sensitive Nodes
Use Layers – four layer board stack-up plan
Top: All high power parts and high
di
/
dt paths, signals that can be routed away from high di/dt paths
Mid1: Ground PlaneMid2: Ground Plane / Power Plane / Signal & low power tracesBottom: low power and signal traces
Flood unused area with copper for improved thermal performance and shieldingPlace and RouteKeep all bypass caps close to pins The higher the impedance and/or gain, the smaller the node should be, especially inputs to op-amps: FB pin, comp pin, etcLow impedance nodes can be wide, such as VIN and VOUT
53Slide54
Protect EMI Sensitive Nodes – Cont.
Make long runs to low impedance nodes, short runs to high impedance nodes. Apply to
Place output voltage divider close to the FB node (high impedance), farther from Vout (low impedance), if have to choose
54
√
×
Route Sense+/Sense- traces parallel to one another – minimize differential-mode noise pickup. Apply to
Current sensing traces
Voltage remote sense lines
Keep sensitive small signal traces thin and further away from
surrounding signals
– lower capacitance couplingSlide55
Customer Layout Example
LM20k 5A Buck regulator
55
SW
L
Res Divider
FB trace
Identified layout problems
Vout sensing point is right under the inductor – noise pick up
FB trace route very close to SW node and di/dt loop – noise coupling
55Slide56
Customer Layout Example
More problems in this layout
56
GND
CIN
GND
CIN GND to LS source path (high di/dt) undefined, through gnd plane
AVIN bypass cap gnd return path very long
Comp network close to high di/dt loop
PGND pins
COMP RC
AVINSlide57
Check List
If your board can not pass Radiated EMI
Check high di/dt loop layout, especially CIN gnd to LS FET source connection
Check GND shielding
Suggest Shielded L
Use twisted pair at input / output (where switching current exists)
Suggest to reduce f
sw or switch transition rateConsider adding conducted EMI filter (also alleviate Radiated EMI)
If your board is not working properly (no schematic reason) or too much voltage spikes, checkHigh di/dt loop layout
GND shielding Sensitive nodes layout, especially FB divider and routingSensitive node groundingBypass caps
Add small bypass caps (e.g. 47nF) to Vin and Vout as close as possibleAdd snubber to SW node
57Slide58
58
AGENDA
Conducted EMI and EMI Filters
EMI Overview – definition and standards
Noise Sources Identification
Minimize
Noise
Generation
by
Layout
Protect
Sensitive Circuits
from
Noise
Snubbers
and Components
Summary
Slide59
DM Conducted EMI
Differential Mode Conducted EMI
In DC-DC converter topology, only Hot and Neutral lines, no CM EMI involved
Involves the Normal Operation of the Circuit
Does not involve Parasitics, except input / output CAP ESR and ESL
Only Related to CURRENT, not voltage
For example, with the same power level Buck converter, lower input voltage means higher input current, thus worse conducted EMI
Why we care?Excessive Input and/or Output Voltage Ripples can compromise operation of Supply and/or Load
59
Switch Mode Power Supply
Supply
LOAD
ISlide60
DM Conducted EMI Mitigation
EMI filter designAdd filter to prevent noise conducted to Supply or Load
May affect SMPS stability
Application Note “Simple Success With Conducted EMI From DC-DC Converters”
60
Switch Mode Power Supply
Supply
LOAD
(
Buck)
60Slide61
EMI LC Filter Design
METHOD 1Measure input voltage ripple
METHOD 2
Approximate
I
IN as a square wave
Find first harmonic amplitude, I, using Fourier
61
Estimate required attenuation
D = duty cycle, V
MAX = required voltage level in dBSlide62
EMI LC Filter Design
Select L
f
Usually in 1uH to 10uH range
Select highest
L
f for input current ratingSelect C
fSelect highest value of C
fa and Cfb
Add
CdReduces output impedance to minimize affect on control loop
62
C
fa
ensures
f
r
of filter is 1 decade below
f
s
C
fb
ensures filter meets attenuation requirementsSlide63
Example, LMZ23605 EVM
63
Initial EMI measurement
Estimated noise level: 80dB
m
V
Required noise level: <40dB
m
VRequired attenuation: 40dBmV
>
80dBμVSlide64
Example, LMZ23605 EVM
Filter Design
C
IN
= 20
μ
Ff
s = 800kHz|Att|dB = 40dBSelect
Lf = 1.0μH
Calculate Cfa and
CfbSelect highest value
Calculate
C
d
64Slide65
Example, LMZ23605 EVM
65
LC Filter Gain
Final EMI measurement
Required Attention
40dB
Selected
L
f
1
μ
F
Calculated
C
fa
4.9
μ
F
Calculated
C
fb
3.9
μ
F
Selected
C
f
4.7
μ
F
C
d
150
μ
F
Frequency - kHz
Gain - dBSlide66
Conducted EMI Before and After Filter
24V input, 12V output, 3A, 320kHz
24V input, 12V output, 3A, 320kHz, w/ filter: 3.3uH, 20uF
66
> 80dB
μ
V
52dB
μ
V
f
sw
= 320kHz
filter
66
0
-20
-40
-60
-80
-100Slide67
67
AGENDA
Snubbers
and Components
EMI Overview – definition and standards
Noise Sources Identification
Minimize
EMI
Generation
by
Layout
Protect
Sensitive Circuits
from
Noise
Conducted EMI and EMI Filters
Summary
Slide68
68
Lower EMI can be achieved by…
Use
snubbers
and
clamps
to minimize both dv/dt and di/dt of switching waveforms
Typical snubbers in switching power suppliesSlide69
Designing RC Snubbers
RC to damp out ringingDetermine
C
SNUB
Measure
f
ring at the switch nodeSelect C that halves
fringCalculate parasitic capacitance,
CP, and leakage inductance, L
lkg
5ns/div
f
ring
= 200MHz
C
SNUB
= 330pFSlide70
C
P
110pF,
L
lkg = 5.4nH
Determine RSNUB
for critical dampingR = characteristic impedance of
LC
Determine
Power Dissipation
Designing RC Snubbers
C
SNUB
R
SNUB
C
SNUB
R
SNUB
R
SNUB
=7.3
Ω
V
PK
= 8V
Valid for
t
rise
<< R
SNUB
C
SNUB
<<
t
ONSlide71
Guidelines to designing RCD Snubber
Rise time controlSelect C, based on:
max current, voltage capacitor charges to and desired rise time.
Select R with time constant much smaller than switching period
Estimate power dissipationSlide72
Guidelines to designing RCD Snubber
Clamp modeSelect C
Select R
Calculate power dissipation
L
=
L
lkg
(flyback) or
L
mag
(forward)
ΔV
= voltage change on
C
SNUB
V
= Initial voltage
i.e
voltage
R
SNUB
is connected to
I
PRIM
= current in
L
at turn offSlide73
Well-Chosen Components/Packages
Reduce Amplitude of Ringing Waveforms
73
Resistors/Capacitors
Inductors/Transformers
Power MOSFETs
Rectifier Diodes
Concerns with components dealing with high
di
/
dt
and
dv
/
dt
stresses
Cin
,
Cout
, FET decoupling,
snubbers
, sense resistors
Biggest concern is stray inductance
Surface mount parts have less inductance than through-hole
Use
Low inductance resistors for current sense applications to preserve waveform shape
Avoid Using Wirewound ResistorsSlide74
Well-Chosen Components/Packages
Reduce Amplitude of Ringing Waveforms
74
Resistors/Capacitors
Inductors/Transformers
Power MOSFETs
Rectifier Diodes
Use shielded inductors for all power inductor paths
If cannot find shielded coupled inductor, specify two shielded inductors
Transformers major problem in EMI
Flyback voltages can be very high
Reflected voltages must be snubbed
Different cores have different leakage flux
Work with a reputable transformer manufacturer such as Pulse or
Coilcraft
to ensure quiet transformer design Slide75
Well-Chosen Components/Packages
Reduce Amplitude of Ringing Waveforms
75
Resistors/Capacitors
Inductors/Transformers
Power MOSFETs
Rectifier Diodes
Come in many packages (TO-220, SO-8, DPAK, etc)
Surface mount devices have EMI advantages
Lower lead inductance
Use copper traces to cool part and
reduce EMI
Through-hole cooled via insulator
which creates parasitic capacitance
and radiates during switching cycles
Method to reduce this noise shown
using faraday shield
Drain-
heatsink
(chassis) capacitance of thru-hole components and its neutralization with a Faraday screen.Slide76
Well-Chosen Components/Packages
Reduce Amplitude of Ringing Waveforms
76
Resistors/Capacitors
Inductors/Transformers
Power MOSFETs
Rectifier Diodes
Used as freewheeling diodes in asynchronous bucks, secondary side rectifiers for transformer-based topologies, voltage doublers, valley fill circuits, etc.
Same package concerns as FETs
Budget space for RC snubber across diodes
Several different types
General purpose – High reverse voltage but too slow for SMPS
Schottky – Low
Vf
, very fast but limited to <100V apps
Ultra and super fast – High
Vr
, fast recovery, low leakage, but high
VfSlide77
Reverse recovery effects EMI
77
Resistors/Capacitors
Inductors/Transformers
Power MOSFETs
Rectifier Diodes
Main trade-off
Faster recovery = higher efficiency but higher EMI
Use Schottky diodes for best performance (low capacitive types like MBR series even better)Slide78
78
AGENDA
Summary
EMI Overview – definition and standards
Noise Sources Identification
Minimize
EMI
Generation
by
Layout
Protect
Sensitive Circuits
from
Noise
Conducted EMI and EMI Filters
Summary
Slide79
SUMMARY
EMI is Electromagnetic Interference. There are many EMC standards, based on regions and applicationsSMPSs are big source of radiated and conducted EMI
EMI comes from high power switching action
EMI problems can be mitigated by identifying high di/dt loop and reducing loop area by careful board layout
Sensitive circuits should be protected with careful layout and shielding
Filters can be designed to attenuate conducted EMI to protect supply / Load
Filters also help reduce radiated EMI79