CS 429H Systems I Instructor Emmett Witchel Today Machine Programming I Basics History of Intel processors and architectures C assembly machine code Assembly Basics Registers operands move ID: 568660
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Slide1
Machine-Level Programming I: BasicsCS 429H: Systems I
Instructor:
Emmett
WitchelSlide2
Today: Machine Programming I: BasicsHistory of Intel processors and architectures
C, assembly, machine code
Assembly Basics: Registers, operands, moveSlide3
Intel x86 Processors
Totally
dominate laptop/desktop/server market
Evolutionary design
Backwards compatible up until 8086, introduced in 1978
Added more features as time goes on
Complex instruction set computer
(CISC)
Many different instructions with many different formats
But, only small subset encountered with Linux programs
Hard to match performance of Reduced Instruction Set Computers (RISC)
But, Intel has done just that
!
In terms of speed. Less so for low power.Slide4
Intel x86 Evolution: Milestones
Name
Date
Transistors MHz
8086 1978
29K 5-10
First 16-bit
processor. Basis for IBM PC & DOS
1MB
address
space
386 1985
275K 16-33
First 32 bit processor , referred to as IA32
Added
“flat addressing”
Capable of running Unix
32-bit
Linux/
gcc
uses no instructions introduced in later
models
Pentium 4F 2004 125M 2800-3800
First 64-bit processor, referred to as x86-64
Core i7 2008 731M
2667-3333Slide5
Intel x86 Processors: Overview
X86-64 /
EM64t
X86-32/IA32
X86-16
8086
286
386
486
Pentium
Pentium MMX
Pentium III
Pentium 4
Pentium 4E
Pentium 4F
Core 2
Duo
Core i7
IA:
often redefined as latest Intel architecture
time
Architectures
Processors
MMX
SSE
SSE2SSE3
SSE4Slide6
Intel x86 Processors, contd.
Machine Evolution
386
1985
0.3M
Pentium 1993 3.1M
Pentium/MMX 1997 4.5M
PentiumPro
1995 6.5MPentium III 1999 8.2MPentium 4 2001 42M
Core 2 Duo 2006 291MCore i7 2008 731M
Added FeaturesInstructions to support multimedia operationsParallel operations on 1, 2, and 4-byte data, both integer & FP
Instructions to enable more efficient conditional operationsLinux/GCC EvolutionTwo major steps: 1) support 32-bit 386. 2) support 64-bit x86-64Slide7
More InformationIntel processors (Wikipedia
)
Intel
microarchitecturesSlide8
New Species: ia64, then IPF, then Itanium
Name
Date
Transistors
Itanium 2001 10M
First shot at 64-bit architecture: first called IA64
Radically new instruction set designed for high performance
Can run existing
IA32
programs
On-board “x86 engine”
Joint project with Hewlett-Packard
Itanium 2 2002 221M
Big performance boostItanium 2 Dual-Core 2006 1.7BItanium has not taken off in marketplaceLack of backward
compatibility, no good compiler support, Pentium 4 got too goodSlide9
x86 Clones: Advanced Micro Devices (AMD)
Historically
AMD has followed just behind Intel
A little bit slower, a lot cheaper
Then
Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies
Built
Opteron
: tough competitor to Pentium 4
Developed x86-64, their own extension to 64 bitsSlide10
Intel’s 64-Bit
Intel Attempted Radical Shift from IA32 to IA64
Totally different
architecture (Itanium)
Executes
IA32
code only as legacy
Performance disappointing
AMD Stepped in with Evolutionary Solution
x86-64 (now called “AMD64”)
Intel Felt Obligated to Focus on IA64
Hard to admit mistake or that AMD is better2004: Intel Announces EM64T extension to IA32Extended Memory 64-bit TechnologyAlmost identical to x86-64!All but low-end x86 processors support x86-64But, lots of code still runs in 32-bit modeSlide11
Our CoverageIA32The traditional x86
x86-64/EM64T
The emerging standard
Presentation
Book
presents IA32 in Sections 3.1—3.12
Covers x86-64 in 3.13Slide12
Today: Machine Programming I: BasicsHistory of Intel processors and architectures
C, assembly, machine code
Assembly Basics: Registers, operands, moveSlide13
Definitions
Architecture:
(also instruction set architecture: ISA) The parts of a processor design that one needs to understand to write assembly code.
Examples:
instruction set specification, registers.
Microarchitecture
:
Implementation of the architecture.
Examples: cache sizes and core frequency.
Example ISAs (Intel): x86, IA, IPFSlide14
CPU
Assembly Programmer’s View
Programmer-Visible State
PC: Program
c
ounter
Address of next instruction
Called “EIP” (IA32) or “RIP” (x86-64)
Register
file
Heavily used program data
Condition
codes
Store status information about most recent arithmetic operation
Used for conditional branching
MemoryByte addressable arrayCode, user data, (some) OS data
Includes stack used to support procedures
PC
RegistersMemoryObject Code
Program DataOS Data
Addresses
Data
Instructions
Stack
Condition
CodesSlide15
Program to Process
We write a program in e.g.,
C
.
A compiler turns that program into an instruction list.
The CPU interprets the instruction list (which is more a graph of basic blocks).
void X (int b) {
if(b == 1) {
…
int main() {
int a = 2;
X(a);
}Slide16
Process in Memory
Program to process.
void X (int b) {
if(b == 1) {
…
int main() {
int a = 2;
X(a);
}
What you wrote
What is in memory.
void X (int b) {
if(b == 1) {
…
int main() {
int a = 2;
X(a);
}
Code
main; a = 2
X; b = 2
Heap
Stack
What must the OS track for a process?Slide17
pid = 127
open files = “.history”
last_cpu = 0
pid = 128
open files = “.history”
last_cpu = 0
A shell forks and execs a calculator
int pid = fork();
if(pid == 0) {
close(“.history”);
exec(“/bin/calc”);
} else {
wait(pid);
int pid = fork();
if(pid == 0) {
close(“.history”);
exec(“/bin/calc”);
} else {
wait(pid);
Process Control
Blocks (PCBs)
OS
USER
int pid = fork();
if(pid == 0) {
close(“.history”);
exec(“/bin/calc”);
} else {
wait(pid);
int calc_main(){
int q = 7;
do_init();
ln = get_input();
exec_in(ln);
pid = 128
open files =
last_cpu = 0
int pid = fork();
if(pid == 0) {
close(“.history”);
exec(“/bin/calc”);
} else {
wait(pid);Slide18
pid = 127
open files = “.history”
last_cpu = 0
pid = 128
open files = “.history”
last_cpu = 0
A shell forks and then execs a calculator
int shell_main() {
int a = 2;
…
Code
main; a = 2
Heap
Stack
0xFC0933CA
int shell_main() {
int a = 2;
…
Code
main; a = 2
Heap
Stack
0xFC0933CA
int calc_main() {
int q = 7;
…
Code
Heap
Stack
0x43178050
pid = 128
open files =
last_cpu = 0
Process Control
Blocks (PCBs)
OS
USERSlide19
Anatomy of an address space
Code
Header
Initialized data
Executable File
Code
Initialized data
Heap
Stack
DLL’s
mapped segments
Process’s
address space
InaccessibleSlide20
text
text
binary
binary
Compiler (
gcc
-S
)
Assembler (
gcc
or
as
)
Linker (
gcc
or
ld
)C program (p1.c p2.c)
Asm program (p1.s p2.s)
Object program (p1.o p2.o)
Executable program (
p)
Static libraries (
.a
)
Turning C into Object Code
Code in files
p1
.c p2.c
Compile with command:
gcc
–O1
p1.c p2.c -o p
Use
basic optimizations
(
-
O1
)
Put resulting binary in file
pSlide21
Compiling Into Assembly
C Code
int
sum(int
x
,
int
y
)
{
int
t = x+y;
return t
;}
Generated IA32 Assembly
sum: pushl %ebp
movl %esp,%ebp
movl 12(%ebp),%eax
addl 8(%ebp),%eax
popl
%ebp ret
Obtain with command
/usr/local/bin/gcc –O1 -S code.cProduces file code.s
Some compilers use
instruction
“
leave
”Slide22
Assembly Characteristics: Data Types
“
Integer” data of 1, 2, or 4 bytes
Data values
Addresses (
untyped
pointers)
Floating
point data of 4, 8, or 10 bytes
No
aggregate types such as arrays or structures
Just contiguously allocated bytes in memorySlide23
Assembly Characteristics: Operations
Perform
arithmetic function on register or memory data
Transfer
data between memory and register
Load data from memory into register
Store register data into memory
Transfer
control
Unconditional jumps to/from procedures
Conditional branchesSlide24
Code for
sum
0x401040 <sum>
:
0x55
0x89
0xe5
0x8b
0x45
0x0c
0x03
0x45
0x08
0x5d
0xc3
Object Code
Assembler
Translates
.s into .oBinary encoding of each instructionNearly-complete image of executable codeMissing linkages between code in different filesLinkerResolves references between filesCombines with static run-time librariesE.g., code for malloc, printf
Some libraries are dynamically linkedLinking occurs when program begins executionTotal of 11
bytesEach instruction 1, 2, or 3 bytesStarts at address
0x401040Slide25
Machine Instruction Example
C Code
Add two signed integers
Assembly
Add 2 4-byte integers
“Long” words in GCC parlance
Same instruction whether signed or unsigned
Operands:
x
:
Register
%
eax
y: Memory M[
%ebp+8]t: Register
%eax
Return function value in
%eaxObject Code3-byte instructionStored at address
0x80483caint t = x+y;
addl 8(%ebp),%eax
0x80483ca: 03 45 08
Similar to expression:
x
+= yMore precisely:
int eax;
int *ebp;eax += ebp[2]Slide26
Disassembled
Disassembling Object Code
Disassembler
objdump
-d p
Useful tool for examining object code
Analyzes bit pattern of series of instructions
Produces approximate rendition of assembly code
Can be run on either
a.out
(complete executable) or
.o
file
080483c4 <sum>:
80483c4: 55 push %ebp
80483c5: 89 e5 mov
%esp,%ebp
80483c7: 8b 45 0c mov 0xc(%ebp),%eax 80483ca: 03 45 08 add 0x8(%ebp),%eax
80483cd: 5d pop %ebp 80483ce: c3 ret Slide27
Disassembled
Dump of assembler code for function sum:
0x080483c4 <sum+0>: push %
ebp
0x080483c5 <sum+1>:
mov
%
esp,%ebp
0x080483c7 <sum+3>:
mov
0xc(%
ebp
),%
eax
0x080483ca <sum+6>: add 0x8(%
ebp),%
eax
0x080483cd <sum+9>: pop %ebp0x080483ce <sum+10>: ret
Alternate DisassemblyWithin gdb Debuggergdb pdisassemble sumDisassemble procedurex/11xb
sumExamine the 11 bytes starting at sumObject
0x401040:
0x55
0x89 0xe5
0x8b 0x45
0x0c 0x03
0x45 0x08 0x5d 0xc3Slide28
What Can be Disassembled?
Anything that can be interpreted as executable code
Disassembler
examines bytes and reconstructs assembly source
%
objdump
-
d
WINWORD.EXE
WINWORD.EXE:
file
format pei-i386
No symbols in "WINWORD.EXE".
Disassembly of section .text:
30001000 <.text>:
30001000
: 55 push %
ebp30001001: 8b ec
mov %esp,%ebp30001003: 6a ff push $0xffffffff
30001005: 68 90 10 00 30 push $0x300010903000100a: 68 91 dc 4c 30 push
$0x304cdc91Slide29
Today: Machine Programming I: BasicsHistory of Intel processors and architectures
C, assembly, machine code
Assembly Basics: Registers, operands, moveSlide30
Integer Registers (IA32)
%
eax
%
ecx
%
edx
%ebx
%esi
%edi
%esp
%ebp
%ax
%
cx
%
dx
%
bx
%
si
%
di
%sp
%
bp
%ah
%
ch
%dh
%
bh
%al
%
cl
%dl
%
bl
16-bit virtual registers
(backwards compatibility)
general purpose
accumulate
counter
data
base
source
index
destination
index
stack
pointer
base
pointer
Origin
(mostly obsolete)Slide31
Moving Data: IA32
Moving Data
movl
Source
,
Dest
:
Operand
Types
Immediate:
Constant integer dataExample: $0x400, $-533Like C constant, but prefixed with
‘$’Encoded with 1, 2, or 4 bytesRegister: One of 8 integer registers
Example: %eax, %edx
But %esp and
%ebp reserved for special use
Others have special uses for particular instructionsMemory: 4 consecutive bytes of memory at address given by register
Simplest example: (%eax)Various other “address modes”
%eax%ecx
%edx
%ebx
%esi
%edi
%esp
%ebpSlide32
movl Operand Combinations
Cannot do memory-memory transfer with a single instruction
movl
Imm
Reg
Mem
Reg
Mem
Reg
Mem
Reg
Source
Dest
C Analog
movl $0x4,%eax
temp = 0x4;
movl $-147,(%eax)
*p = -147;
movl %eax,%edx
temp2 = temp1;
movl
%
eax
,(%
edx
)
*p = temp;
movl (%eax),%edx
temp = *p;
Src,DestSlide33
Simple Memory Addressing Modes
Normal (
R)
Mem[Reg[R
]]
Register R specifies memory address
movl
(%
ecx
),%
eax
Displacement D(R)
Mem[Reg[R]+D]
Register R specifies start of memory regionConstant displacement D specifies offsetmovl
8(%ebp),%edxSlide34
Using Simple Addressing Modes
void
swap(int
*
xp
,
int
*
yp
)
{
int
t0 = *xp;
int t1 = *yp
; *
xp = t1;
*yp = t0;}
Body
SetUp
Finish
swap:
pushl
%ebp
movl %esp,%ebp
pushl %ebx
movl
8(%ebp), %
edx
movl
12(%ebp), %
ecx
movl
(%
edx
), %
ebx
movl
(%
ecx
), %
eax
movl
%
eax
, (%
edx
)
movl
%
ebx
, (%
ecx
)
popl
%
ebx
popl
%
ebp
retSlide35
Using Simple Addressing Modes
void
swap(int
*
xp
,
int
*
yp
)
{
int t0 = *
xp; int
t1 = *yp; *
xp = t1;
*yp = t0;
}
swap: pushl %ebp
movl %esp,%ebp pushl
%ebx
movl
8(%ebp), %edx
movl 12(%ebp), %
ecx movl
(%edx), %ebx movl (%ecx), %eax
movl
%
eax
, (%
edx
)
movl
%
ebx
, (%
ecx
)
popl
%
ebx
popl
%
ebp
ret
Body
Set
Up
FinishSlide36
Understanding Swap
void swap(int *xp, int *yp)
{
int t0 = *xp;
int t1 = *yp;
*xp = t1;
*yp = t0;
}
Stack
(in memory)
Register
Value
%
edx
xp
%
ecx
yp%ebx t0%eax t1
yp
xp
Rtn
adr
Old %
ebp
%ebp
0
4
8
12
Offset
•
•
•
Old %
ebx
-4
%
esp
movl
8(%
ebp
), %
edx
#
edx
=
xp
movl
12(%
ebp
), %
ecx
#
ecx
=
yp
movl
(%
edx
), %
ebx
#
ebx
= *
xp
(t0)
movl
(%
ecx
), %
eax
#
eax
= *yp (t1)
movl
%
eax
, (%
edx
) # *
xp
= t1
movl
%
ebx
, (%
ecx) # *yp = t0Slide37
Understanding Swap
0x120
0x124
Rtn
adr
%ebp
0
4
8
12
Offset
-4
123
456
Address
0x124
0x120
0x11c
0x118
0x114
0x110
0x10c
0x108
0x104
0x100
yp
xp
%eax
%
edx
%
ecx
%ebx
%esi
%edi
%esp
%ebp
0x104
movl
8(%
ebp
), %
edx
#
edx
=
xp
movl
12(%
ebp
), %
ecx
#
ecx
=
yp
movl
(%
edx
), %
ebx
#
ebx
= *
xp
(t0)
movl
(%
ecx
), %
eax
#
eax
= *
yp
(t1)
movl
%
eax
, (%
edx
) # *
xp
= t1
movl
%
ebx
, (%
ecx
) # *
yp
= t0Slide38
Understanding Swap
0x120
0x124
Rtn
adr
%ebp
0
4
8
12
Offset
-4
123
456
Address
0x124
0x120
0x11c
0x118
0x114
0x110
0x10c
0x108
0x104
0x100
yp
xp
%eax
%
edx
%ecx
%ebx
%esi
%edi
%
esp
%ebp
0x124
0x104
0x120
movl
8(%
ebp
), %
edx
#
edx
=
xp
movl
12(%
ebp
), %
ecx
#
ecx
=
yp
movl
(%
edx
), %
ebx
#
ebx
= *
xp
(t0)
movl
(%
ecx
), %
eax
#
eax
= *
yp
(t1)
movl
%
eax
, (%
edx
) # *
xp
= t1
movl
%
ebx
, (%
ecx
) # *
yp
= t0Slide39
Understanding Swap
0x120
0x124
Rtn
adr
%ebp
0
4
8
12
Offset
-4
123
456
Address
0x124
0x120
0x11c
0x118
0x114
0x110
0x10c
0x108
0x104
0x100
yp
xp
%eax
%edx
%ecx
%ebx
%esi
%edi
%esp
%ebp
0x120
0x104
0x124
0x124
movl
8(%
ebp
), %
edx
#
edx
=
xp
movl
12(%
ebp
), %
ecx
#
ecx
=
yp
movl
(%
edx
), %
ebx
#
ebx
= *
xp
(t0)
movl
(%
ecx
), %
eax
#
eax
= *
yp
(t1)
movl
%
eax
, (%
edx
) # *
xp
= t1
movl
%
ebx
, (%
ecx
) # *
yp
= t0Slide40
456
Understanding Swap
0x120
0x124
Rtn
adr
%ebp
0
4
8
12
Offset
-4
123
456
Address
0x124
0x120
0x11c
0x118
0x114
0x110
0x10c
0x108
0x104
0x100
yp
xp
%eax
%edx
%ecx
%ebx
%esi
%edi
%
esp
%ebp
0x124
0x120
123
0x104
movl
8(%
ebp
), %
edx
#
edx
=
xp
movl
12(%
ebp
), %
ecx
#
ecx
=
yp
movl
(%
edx
), %
ebx
#
ebx
= *
xp
(t0)
movl
(%
ecx
), %
eax
#
eax
= *
yp
(t1)
movl
%
eax
, (%
edx
) # *
xp
= t1
movl
%
ebx
, (%
ecx
) # *
yp
= t0Slide41
Understanding Swap
0x120
0x124
Rtn
adr
%ebp
0
4
8
12
Offset
-4
123
456
Address
0x124
0x120
0x11c
0x118
0x114
0x110
0x10c
0x108
0x104
0x100
yp
xp
%eax
%edx
%ecx
%ebx
%esi
%edi
%esp
%ebp
456
0x124
0x120
0x104
123
123
movl
8(%
ebp
), %
edx
#
edx
=
xp
movl
12(%
ebp
), %
ecx
#
ecx
=
yp
movl
(%
edx
), %
ebx
#
ebx
= *
xp
(t0)
movl
(%
ecx
), %
eax
#
eax
= *
yp
(t1)
movl
%
eax
, (%
edx
) # *
xp
= t1
movl
%
ebx
, (%
ecx
) # *
yp
= t0Slide42
456
456
Understanding Swap
0x120
0x124
Rtn
adr
%ebp
0
4
8
12
Offset
-4
Address
0x124
0x120
0x11c
0x118
0x114
0x110
0x10c
0x108
0x104
0x100
yp
xp
%eax
%edx
%ecx
%ebx
%esi
%edi
%
esp
%ebp
456
456
0x124
0x120
123
0x104
123
movl
8(%
ebp
), %
edx
#
edx
=
xp
movl
12(%
ebp
), %
ecx
#
ecx
=
yp
movl
(%
edx
), %
ebx
#
ebx
= *
xp
(t0)
movl
(%
ecx
), %
eax
#
eax
= *
yp
(t1)
movl
%
eax
, (%
edx
) # *
xp
= t1
movl
%
ebx
, (%
ecx
) # *
yp
= t0Slide43
Understanding Swap
0x120
0x124
Rtn
adr
%ebp
0
4
8
12
Offset
-4
456
123
Address
0x124
0x120
0x11c
0x118
0x114
0x110
0x10c
0x108
0x104
0x100
yp
xp
%eax
%edx
%ecx
%ebx
%esi
%edi
%esp
%ebp
456
0x124
0x120
0x104
123
123
movl
8(%
ebp
), %
edx
#
edx
=
xp
movl
12(%
ebp
), %
ecx
#
ecx
=
yp
movl
(%
edx
), %
ebx
#
ebx
= *
xp
(t0)
movl
(%
ecx
), %
eax
#
eax
= *
yp
(t1)
movl
%
eax
, (%
edx
) # *
xp
= t1
movl
%
ebx
, (%
ecx
) # *
yp
= t0Slide44
Complete Memory Addressing Modes
Most General Form
D(
Rb,Ri,S
)
Mem
[
Reg
[
Rb
]+S*Reg[Ri]+ D]D: Constant “displacement” 1, 2, or 4 bytesRb
: Base register: Any of 8 integer registersRi: Index register: Any, except for %
espUnlikely you’d use %ebp,
eitherS: Scale: 1, 2, 4, or 8 (why these numbers?)
Special Cases
(Rb,Ri)
Mem[Reg[Rb]+Reg[Ri]] D(Rb,Ri
) Mem[Reg[Rb]+Reg[Ri]+D] (Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]]Slide45
Today: Machine Programming I: BasicsHistory of Intel processors and architectures
C, assembly, machine code
Assembly Basics: Registers, operands, move
Intro to x86-64Slide46
Data Representations: IA32 + x86-64
Sizes of C Objects (in Bytes)
C Data
Type Generic
32-
bit
Intel IA32
x86
-64
unsigned 4 4 4
int
4 4 4
long
int
4 4 8
char 1 1 1
short 2 2 2
float 4 4 4
double 8 8 8
long double 8 10/12 16
char * 4 4 8
Or any other pointerSlide47
%rsp
x86-64 Integer Registers
Extend existing registers. Add 8 new ones.
Make
%ebp
/
%rbp
general purpose
%eax
%ebx
%ecx
%edx
%esi
%edi
%esp
%ebp
%r8d
%r9d
%r10d
%r11d
%r12d
%r13d
%r14d
%r15d
%r8
%r9
%r10
%r11
%r12
%r13
%r14
%r15
%
rax
%
rbx
%rcx
%rdx
%rsi
%rdi
%rbpSlide48
InstructionsLong word
l
(4 Bytes) ↔ Quad word
q
(8 Bytes)
New instructions:
movl
➙
movq
addl
➙
addq
sall ➙ salqetc.
32-bit instructions that generate 32-bit resultsSet higher order bits of destination register to 0Example: addlSlide49
32-bit code for swap
void
swap(int
*
xp
,
int
*
yp
)
{
int
t0 = *xp; int
t1 = *yp; *
xp = t1;
*yp = t0;
}
Body
SetUp
Finish
swap: pushl
%ebp
movl %esp,%ebp
pushl %ebx
movl 8(%ebp), %edx
movl
12(%
ebp
), %
ecx
movl
(%
edx
), %
ebx
movl
(%
ecx
), %
eax
movl
%
eax
, (%
edx
)
movl
%
ebx
, (%
ecx
)
popl
%
ebx
popl
%
ebp
retSlide50
64-bit code for swap
Operands passed in registers (why useful?)
First (
xp
) in
%
rdi
, second (
yp
) in
%
rsi
64-bit pointersNo stack operations required32-bit dataData held in registers %
eax and %edx
movl operation
void
swap(int
*xp, int *yp)
{ int t0 = *xp; int t1 = *yp;
*xp = t1; *yp = t0;}
Body
Set
Up
Finish
swap:
movl
(%
rdi
), %
edx
movl
(%
rsi
), %
eax
movl
%
eax
, (%
rdi
)
movl
%
edx
, (%
rsi
)
retSlide51
64-bit code for long int swap
64-bit data
Data held in registers
%
rax
and
%
rdx
mov
q
operation
“q” stands for quad-word
void swap(long
*xp,
long *yp)
{
long t0 = *xp;
long t1 = *yp; *xp = t1; *yp = t0;
}
Body
Set
Up
Finish
swap_l
: movq (%rdi), %
rdx
movq
(%
rsi
), %
rax
movq
%
rax
, (%
rdi
)
movq
%
rdx
, (%
rsi
)
retSlide52
Machine Programming I: SummaryHistory of Intel processors and architectures
Evolutionary design leads to many quirks and artifacts
C, assembly, machine code
Compiler must transform statements, expressions, procedures into low-level instruction sequences
Assembly Basics: Registers, operands, move
The x86 move instructions cover wide range of data movement forms
Intro to x86-64
A major departure from the style of code seen in IA32