PDF-POST OFFICE BOX 655303 DALLAS, TEXAS 75265 HOUSTON, TEXAS 772511443W

SLCS122A PACKAGE TA max AT 25. They perform the Boolean functions Y A B or Y A B in positive logic The SN54ALS02A and SN54AS02 are characterized for operation over the full military temperature range of 872255 C to 125 C The SN74ALS02A and SN74AS02 are characterized for operat 5 V to 36 V TTL and CMOSCompatible HighImpedance DiodeClamped Inputs Separate InputLogic Supply Thermal Shutdown Internal ESD Protection Input Hysteresis Improves Noise Immunity 3State Outputs Minimized Power Dissipation SinkSource Interlock Circuitr Products conform to specifications per the terms of Te xas Instruments standard warranty Production processing does not necessarily include testing of all parameters BW 87223 dB 70 MHz Matched 05dB Attenuators for Contrast Control Three Externall The strobe G input must be at a low logic level to enable the data selectionmultiplexing function A high level at the strobe terminal forces the W output high and the Y output low The SN54F151B is characterized for operation over the full military The AS850A has a clockcontrolled select register allowing for a symmetrical presentation of the select inputs to the decoder while the AS851B has an enablecontrolled select register allowing the user to select and hold one particular data line A buf 15 CP 0 15 CG 0 15 CO 1 2 4 8 This symbol is in accordance with ANSIIEEE Std 911984 and IEC Publication 61712 4 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A B GND GND GND GND CC CC S0 S1 S2 S3 DW PACKAGE TOP VIEW EPIC is a trademark Products conform to specifications per the terms of Te xas Instruments standard warranty Production processing does not necessarily include testing of all parameters BW 87223 dB 70 MHz Matched 05dB Attenuators for Contrast Control Three Externall The AS850A has a clockcontrolled select register allowing for a symmetrical presentation of the select inputs to the decoder while the AS851B has an enablecontrolled select register allowing the user to select and hold one particular data line A buf In highperformance memory systems this decoder can be used to minimize the effects of system decoding When employed with highspeed memories utilizing a fast enable circuit the delay times of this decoder and the enable time of the memory are usually The strobe G input must be at a low logic level to enable the data selectionmultiplexing function A high level at the strobe terminal forces the W output high and the Y output low The SN54F151B is characterized for operation over the full military 

 

 SDLS085  Copyright 1988, Texas Instruments Incorporated+2&(3&$$&!'40 

 

SDLS085  POST OFFICE BOX 655303 DALLAS, TEXAS 75265 
   SCAS042B  MAY 1988  1 , G2B eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates orinverters when expanding. A 24-l
  
      
    
SLLS455C  Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o   SCLS584A  MAY 2004  1 flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. The carry look-ahead circuitry provides for cascading