isthepermittivityofthegatedielectricisthepermittivityofspacermaterialisthewidthoftheMOSstructureandisthegatedielectricthicknessSince001893832000 ID: 504343
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IEEETRANSACTIONSONELECTRONDEVICES,VOL.53,NO.4,APRIL2006CompactModelingoftheEffectsofParasiticInternalFringeCapacitanceontheThresholdVoltageofGate-DielectricNanoscaleSOIMOSFETsM.JagadeshKumar, ,SumeetKumarGupta, ,andVivekVenkataraman, Acompactmodelfortheeffectoftheparasiticin-ternalfringecapacitanceonthethresholdvoltageofhigh-dielectricsilicon-on-insulatorMOSFETsisdeveloped.Theauthorsmodelincludestheeffectsofthegate-dielectricpermit-tivity,spaceroxidepermittivity,spacerwidth,gatelength,andthe isthepermittivityofthegatedielectric,isthepermittivityofspacermaterial,isthewidthoftheMOSstructureandisthegate-dielectricthickness.Since0018-9383/$20.00©2006IEEE :PARASITICINTERNALFRINGECAPACITANCEONGATE-DIELECTRICNANOSCALESOIMOSFETS707 Fig.1.Cross-sectionalviewofanSOIMOSFETshowingtheinternalpara-siticfringecapacitance. Fig.2.FringingÞeldfromthebottomofthegateelectrodetothedrain(orsource).areinseries,thenetinÞnitesimalcapacitancecanbewrittenas Thetotalinternalfringecapacitancecanbeobtainedbyintegrating(1)overthegate-dielectricthicknessas Equation(2)isreÞnedbelowinordertotakecareoftheimperfectcircularityofthefringingÞeldlines.ThemodelbyKamchouchiandZaky[3]givestheparasiticcapacitanceperunitlengthconsideringtheelectricÞeldlinesfringingfromtheentireperimeterofthebottomedgeofthegateelectrodeas for isthegatelength.Thetotalfringecapacitancecanbeobtainedbymultiplying(3)withtheperimeterofthebottomedgeofthegateelectrode[3].SinceweneedtoaccountforelectricÞeldlinesfringingfromthebottomedgeofthegatetoeitherthesourceorthedrainregiononly,theinternalfringecapacitancecanbewrittenas for Itcanbeseenthat(2)reducesto(4)inthelimitbutforaconstantfactor.ThisdifferencearisesbecauseoftheassumptionofthefringingelectricÞeldlinesbeingcircularwhilederiving(2).Thus,(2)ismultipliedbytheabovefactortoobtain Theaboveexpressionreducesto(4)inthelimitTheKamchouchiandZakymodelin(4),andhence(5),assumesthattheseparationbetweentheelectrodesisverysmallincomparisontothelengthoftheelectrodes.Thisiscertainlynotthecaseinshortchannelhigh-dielectricSOIMOSFETs.Hence,(5)isfurthermodiÞedtorepresentthetruepicture.ThefringingÞeldfromthegatetothesource/drainregionsincreasesasafunctionof[1].ThisistheeffectoftheincreasedcrowdingofÞeldlinesinthespacerregionforlargegate-dielectricthicknesses,i.e,forcomparabletoHence,thefringecapacitanceinthespacerregionismorethanwhathasbeenassumedwhilederiving(5).Toaccountforthis,aneffectivespacerdielectricconstantisdeÞnedas Substituting(6)inplaceofin(5),wecanobtaintheÞnalexpressionfortheparasiticinternalfringecapacitanceas (7) IEEETRANSACTIONSONELECTRONDEVICES,VOL.53,NO.4,APRIL2006III.EFFECTOFTHENTERNALAPACITANCEONTHEURFACEOTENTIALToincludetheeffectoftheinternalfringecapacitanceonthesurfacepotential,weassumethechargedistributioninducedinthesourceanddrainregionsduetothefringingelectricÞeldlinesasinauniformlychargedplateasshowninFig.3,withthechargedensitygivenby forthesourceregionforthedrainregionisthebuilt-inpotentialacrossthebodyÐsourcejunction,isthesiliconbandgap,isthebody/substratedopingconcentration,isthethermalvoltage,istheintrinsiccarrierconcentration,arethepotentialsappliedtothegateanddrainelectrodes,respectively,istheßat-bandvoltage,iswidthofthegate,andisthespacerthickness.Thepotentialduetothisuniformchargedistributionisevaluatedalongthechannelatthemiddleofthegatewidthastheeffectismaximumhere.InanMOSFET,theÞeldlinesoriginatingfromthebottomofthechargedplateonlywillcontributetothepotentialinthechannel;therefore,onlyhalfthecoulombpotentialduetothesechargesisconsidered.Then,thepotentialatadistanceÒxÓfromtheuniformlychargedplateisgivenby(Fig.3) isthedielectricconstantofsilicon.Evaluationoftheintegralin(8)givestheexpressionforasgivenin(9)shownatthebottomofthepage.Young[4]proposedamodelforthesurfacepotentialalongthechannel(-directioninFig.1)forafullydepleted(FD)SOIMOSFET,assumingasimpleparabolicpotentialproÞleintheverticaldirection(-directioninFig.1)as Fig.3.Potentialduetoauniformlychargedplate. istheßat-bandvoltage,isthesiliconsubstratethicknessandisthepermittivityofsilicon.Theparametersaregivenas Intheaboveanalysis,wehaveassumedtheburiedoxidethicknesstobelargeandhenceneglectedthecorrespondingThesurfacepotentialminimumisat andisgivenby Toobtainthesurfacepotentialincludingtheeffectoftheinternalfringecapacitance,thepotentialduetothechargesonthesourceanddrainregionsasgivenby(9),isaddedto(10)andtheexpressionforsurfacepotentialismodiÞedas :PARASITICINTERNALFRINGECAPACITANCEONGATE-DIELECTRICNANOSCALESOIMOSFETS709isthepotentialalongthechannelduetothechargesinthesourceregion,andisthepotentialalongthechannelduetothechargesinthedrainregion.TheminimumofthemodiÞedsurfacepotentialisgivenby IV.EFFECTOFTHENTERNALAPACITANCEONTHEOLTAGEIn[5],KumarandChaudhryproposedamodelforthethresholdvoltageofdual-materialgate(DMG)-SOIMOSFETsbyequatingthesurfacepotentialminimumgivenby(11)totwicetheFermipotentiali.e., Themodelin[5]canbemodiÞedforSMGSOIMOSFETsas Toincorporatetheeffectoftheinternalfringecapacitance,wemodify(14)asisasgivenin(13).Solving(16)resultsinthesameexpressionforthethresholdvoltageasgivenin(15),exceptforamodiÞcationintheexpressionforÒÓgivenas Fig.4.Internalfringecapacitancevariationwithgateoxidepermittivityfor;and(b)nm.GatewidthisÞxedat1m,EOTisdependenton[see(9)]andisthevalueof ,thevalueofthresholdvoltagecanbeeasilyobtainedbyiterativelysolving(15).V.SIMULATIONESULTSANDFig.4showsthevariationoftheinternalfringecapacitanceversusthegate-dielectricpermittivityevaluatedus-ingtheproposedmodelandcomparedwithMEDICI[10]simulationsforchannellengthsof60and40nm(seeTableIforadescriptionofthedeviceparameters).ThecapacitanceisextractedfromMEDICIinthefollowingmanner1)thegate,source,anddrainelectrodeheightsaremadenegligiblesothatothercomponentsofthefringecapacitancethatariseduetotheÞniteelectrodethicknessarenulliÞedand2)thetotalcapacitanceasseenfromthegateelectrodeforthisMOSFETstructureisextractedusingthemethodofincremen-talchargeduetothesmallincrementinvoltage.ThisgivesthefringecapacitanceplustheMOSgatecapacitance.Then,issubtractedfromthecapacitanceobtainedabovetoÞndthevalueof.ThereisadifferenceofaboutFbetweenourcalculatedandsimulated IEEETRANSACTIONSONELECTRONDEVICES,VOL.53,NO.4,APRIL2006TABLEISEDINTHEIMULATION Fig.5.Calculatedsurfacepotentialvariationalongthechannelforwithandwithouttheeffectofthefringecapacitance.TheparametersusedV,EOTvalues.ThevaluesoftheidealMOSgatecapacitanceFfor nmand nm.ItcanbeseenintheÞgurethattheparasiticfringecapacitanceincreaseswiththeincreasinggate-dielectricpermittivity.Thisisbecausethephysicalgate-dielectricthick-nessincreasesasthegate-dielectricpermittivityincreases[byafactorof]forthesameequivalentoxidethickness(EOT).ThisresultsinanincreaseinthefringingelectricÞeldlinesfromthebottomofthegateelectrodetothesourceanddrainregions.InFig.5,thevaluesofthesurfacepotentialwithandwithouttheeffectofparasiticfringecapacitanceareplottedagainstthehorizontaldistanceinthechannelforagate-dielectricpermittivityof60.IntheÞgure,itisevidentthatthesurfacepotentialincreasesduetotheeffectofthefringecapacitance,resultinginanincreaseoftheminimumsurfacepotential.Furthermore,itcanbeseenthattheeffectofthispotentialismaximumroughlyatthepointofminimumsurfacepotential;hence,onewouldexpectasigniÞcanteffectofonthethresholdvoltage.Toverifytheproposedmodel,the2-DdevicesimulatorMEDICI[10]wasusedtosimulatethethresholdvoltage.AnFDn-channelSOIstructureisimplementedinMEDICIhavinguniformlydopedsource/drainandbodyregions.This Fig.6.Comparisonofthesimulatedandcalculatedthresholdvoltagevaria-tionversusthegate-dielectricconstantfor(a)withouttheS/D-Gateoverlap;and(b)withtheS/D-Gateoverlap.Theparametersusedare:EOTstructureissimulatedbothwithandwithoutthegate-source/drain(S/D)overlap.InFig.6,thecalculatedvaluesofthethresholdvoltageasafunctionofthegate-dielectricpermittivityarecomparedwiththoseobtainedfromthe2-Dsimulation.AscanbeseenfromtheÞgure,thethresholdvoltageobtainedfromthemodeltracksthesimulationvalueswellwithamaximumoffsetofabout15mV.Themodelgivesagoodagreementwiththesimulationevenforthecaseofthegate-S/Doverlap.Itisevidentthatthethresholdvoltagedecreaseswiththeincreasing.ThisisbecauseoftheincreaseinthesurfacepotentialasaresultofthechargesinducedinthedrainandsourceregionsduetofringingÞeldlinesfromthebottomofthegateelectrode.Thisresultsinanearlyonsetofinversioninthechannelandhencealowerthresholdvoltage.Thedropinthethresholdvoltageisashighasabout60Ð80mVfor increasesfrom3.9to80.ToinvestigatethesigniÞcanceofquantummechanical(QM)effectsintheaboveanalysis,thesimulationswereperformedbyincludingtheQMeffectsinMEDICI[10].InFig.7,thethresholdvoltageobtainedwithandwithoutQMeffectsarecompared.AsisevidentfromtheÞgure,thereisaverysmallandinsigniÞcantdifferencebetweenthetwo,suggestingthat :PARASITICINTERNALFRINGECAPACITANCEONGATE-DIELECTRICNANOSCALESOIMOSFETS711 Fig.7.EffectofincludingQMeffectsinthesimulation.Theparametersusedare:V,EOTtheQMeffectscanbeneglectedinthethresholdvoltageVI.CWehaveexaminedtheeffectsoftheparasiticinternalfringecapacitanceonthethresholdvoltageofFDhigh-MOSFETsbydevelopingasimplemodelfortheinternalfringecapacitanceandobtainingexpressionsforthesurfacepoten-tialandthresholdvoltageincludingtheeffectoftheinternalfringecapacitance.Wehavecomparedtheresultswithaccurate2-Dsimulations.Thecalculatedvaluesofthethresholdvolt-ageobtainedfromtheproposedmodelagreewellwiththesimulatedresults.ThereisasigniÞcantdropinthethresholdvoltageduetofringingÞeldlinesfromthebottomedgeofthegateelectrodetothesourceanddrainregionsforhighergate-dielectricpermittivities(i.e.,higherphysicalgate-dielectricthicknessforthesameeffectiveoxidethickness).ThismayaffectthedevicecharacteristicsandperformancesigniÞcantly;hence,itisimportanttorecognizethiseffectespeciallyforgate-dielectricSOIMOSFETs.Ourmodelcanbeeasilyimplementedinacircuitsimulatortoincludethiseffect.[1]B.Cheng,M.Cao,R.Rao,A.Inani,P.V.Voorde,W.M.Greene,J.M.C.Stork,Y.Zhiping,P.M.Zeitzoff,andJ.C.S.Woo,ÒTheimpactofhigh-gatedielectricsandmetalgateelectrodesonsub-100nm ,vol.46,no.7,pp.1537Ð1544,Jul.1999.[2]A.ChaudhryandM.J.Kumar,ÒControllingshort-channeleffectsindeepsubmicronSOIMOSFETsforimprovedreliability:Areview,Ó ,vol.4,no.1,pp.99Ð109,Mar.2004.[3]H.KamchouchiandA.Zaky,ÒAdirectmethodfortheedgecapacitanceofthickelectrodes,Ó ,vol.8,no.5,pp.1365Ð1371,May1975.[4]K.K.Young,ÒShort-channeleffectinfullydepletedSOIMOSFETÕs,Ó ,vol.36,no.2,pp.399Ð402,Feb.1989.[5]M.J.KumarandA.Chaudhry,ÒTwo-dimensionalanalyticalmodelingoffullydepletedDMGSOIMOSFETandevidencefordiminished ,vol.51,no.4,pp.569Ð574,Apr.2004.[6]G.V.ReddyandM.J.Kumar,ÒAnewdual-materialdouble-gate(DMDG)nanoscaleSOIMOSFETÑtwo-dimensionalanalyticalmodel-ingandsimulation,Ó ,vol.4,no.2,pp.260Ð268,Mar.2005.[7]K.Suzuki,ÒParasiticcapacitanceofsubmicrometerMOSFETs,Ó ,vol.46,no.9,pp.1895Ð1900,Sep.1999.[8]R.ShrivastavaandK.Fitzpatrick,ÒSimplemodelfortheoverlapcapacitanceofaVLSIMOSdevice,Ó vol.ED-29,no.12,pp.1870Ð1875,Dec.1982.[9]N.R.Mohapatra,M.P.Desai,S.G.Narendra,andV.R.Rao,ÒModelingofparasiticcapacitancesindeepsubmicrometerconventionalandhigh-KdielectricMOStransistors,Ó ,vol.50,no.4,pp.959Ð966,Apr.2003.2003. !",TechnologyModelingAssociates,Inc.,PaloAlto,CA, M.JagadeshKumar(MÕ95ÐSMÕ99)wasborninAndhraPradesh,India.HereceivedtheM.S.andPh.D.degreesfromtheIndianInstituteofTechnol-ogy(IIT),Madras,India,allinelectricalengineering.From1991to1994,heperformedpost-doctoralresearchinthemodelingandprocessingofhigh-speedbipolartransistorswiththeDepartmentofElectricalandComputerEngineering,UniversityofWaterloo,Waterloo,ON,Canada,wherehealsodidresearchonamorphoussiliconthin-Þlmtransistors.FromJuly1994toDecember1995,hewasinitiallywiththeDepartmentofElectronicsandElectricalCommunicationEngineering,IIT.HethenjoinedtheDepartmentofElectricalEngineeringofthesameuniversity,wherehebecameanAssociateProfessorinJuly1997andaFullProfessorinJanuary2005.Heisareviewerfordifferentjournalsincluding # $$ % & .Heistheauthorofmore100publicationsinpeer-reviewedjournalsandconferences.HisresearchinterestsincludeVLSIdevicemodelingandsimulationfornanoscaleapplica-tions,ICtechnology,andpowersemiconductordevices.Dr.KumarisaFellowoftheInstituteofElectronicsandTelecommunicationEngineers,India.HisteachinghasoftenbeenratedasoutstandingbytheFacultyAppraisalCommittee,IIT.HewastheChairmanoftheFellowshipCommittee,TheSixteenthInternationalConferenceonVery-Large-Scale-Integration(VLSI)Design,January4Ð8,2003,NewDelhi,India.HewastheChairmanoftheTechnicalCommitteeforHighFrequencyDevices,12thInternationalWorkshoponthePhysicsofSemiconductorDevices,December13Ð17,2005,NewDelhi,India.HeisareviewerforIEEETRANSACTIONSONLECTRON SumeetKumarGupta(SÕ05)iscurrentlyworkingtowardtheB.Tech.degreeinelectricalengineeringattheIndianInstituteofTechnology,Delhi,India.Hiscurrentresearchinterestsincludedevicemodelingandsimulation.Heisalsointerestedinlowpowerverylargescaledesign,andmemorydesignandtesting. VivekVenkataraman(SÕ05)iscurrentlyworkingtowardtheB.Tech.degreeinelectricalengineeringattheIndianInstituteofTechnology,Delhi,India.Hisresearchinterestsincludesemiconductordevicephysics,nanoscaledevicemodelingandsim-ulation,andorganicsemiconductors/electronics.