UCC28740 Feedback Loop Compensation Design - PowerPoint Presentation

Slide1

UCC28740 Feedback Loop Compensation Design

1

Flyback Regulator Schematic Diagram

2

using UCC28740 with Opto-coupled Feedback

TL431

UCC28740 Control Law

3

for Output Voltage Regulation

Control region 1

(FM)

Control region 2

(FM)

Control region 3

(AM)

Control region 4

(FM)

Multiple control regions modify switching frequency and inductor current amplitude to achieve high efficiency over wide output power range.

Control-loop gain factors change when operation moves from one region to another.

Voltage Feedback Loop Block Diagram

4

Control-Loop Gain: AV = G431(s) · GOPTO(S) · GFB1 · GFB2 · KFMn · GPn · ZL(s)

G

Pn

Z

L(s)

K

FMn

G

FB2

G

FB1

G

OPTO

(s)

G

431(s)

i

E

i

FB

i

D

v

O

IOUT + iO

fSW

vCL

V

CSn

VIN

VOUT + vO

in FM Regions of Control Law

n = 1, 2, or 4, depending on FM region of operation

Voltage Feedback Loop Block Diagram

5

Control-Loop Gain: AV = G431(s) · GOPTO(S) · GFB1 · GFB2 · KAM3 · GP3 · ZL(s)

G

P3

Z

L(s)

K

AM

G

FB2

G

FB1

G

OPTO

(s)

G

431(s)

i

E

i

FB

i

D

v

O

IOUT + iO

vCS

vCL

F

AM

VIN

VOUT + vO

in AM Region of Control Law

Gain Blocks Defined – G431(s)

6

TL431

Output voltage sense to

opto

-coupler diode current gain:

i

D

Gain Blocks Defined – GOPTO(s)

7

Opto

-coupler diode current to emitter current gain:

TL431

i

D

i

E

C

CE

is external capacitance added across opto-coupler, if necessary

TL431

Gain Blocks Defined – G

FB1

8

Opto-coupler emitter current to FB-pin current gain:

i

E

i

FB

Gain Blocks Defined – GFB2

9

FB-pin current to Control-Law voltage gain:

i

FB

i

FB

Gain Blocks Defined – KFMn, KAM3

10

Control-Law voltage to power stage modulation (FM or AM) gain:

Gain Blocks Defined – GPn, GP3

11

TL431

Power stage modulation (FM or AM) to average current gain:

I

Pn

= I

PMAX

for n = 4; = I

PMAX/4 for n = 1, 2

I

P

= Primary peak current at specific load condition

F

AM

= AM region switching frequency

Gain Blocks Defined – ZL(s)

12

TL431

Output current to output voltage gain:

Output impedance, Z

L

(s), comprises output capacitance in parallel with load resistance.

Factor of ½ is due to differentiation.

R

L

= V

OUT

/I

OUT

at specific condition of interest.

Full Loop-gain Equation

13

Control-Loop Gain: AV = G431(s) · GOPTO(S) · GFB1 · GFB2 · KFMn · GPn · ZL(s)

Design Considerations

14

Limited flexibility of choice for several component values:REQU = device parameter, inflexible valuePMAX, FMAX, and COUT are determined during DC design RTL and RFB4 have narrow variability after nominal DC design considerationCTR has limited choice of rankingsCP can only be made larger (using external CCE), not smallerRFB1 and CZ have wider range of values to set compensation zero

Design Considerations

15

Generate Bode-plot gain and phase of AV at full-load condition with CZ = 0.From plot, determine the frequency (fZ) where placing a zero in the response would cause the response to cross 0dB with at least 45° phase margin. Calculate CZ = 1/(2πfZRFB1)If necessary, adjust CP with CCE such that the loop cross-over frequency < 3 kHz. Iterate and fine-tune loop compensation during prototype evaluation.

Simplifying Assumptions

16

TL431, CTR

:

The gain of these

components

do have high-frequency r

oll-off characteristics (pole) but

are considered constant provided the loop crossover frequency is significantly lower than

their respective pole frequencies.

R

EQU

is linearized from a piece-wise linear approximation of the V

FB

/I

FB

curve.

The ESR-zero frequency

of

C

OUT

is far above the loop crossover frequency.

C

FB3

is more than 10 times larger than C

P

which causes its effect on compensation to be negligible.

The product

g

M

R

TL

> 10000, which causes several terms to become negligible (

g

M

= transconductance of TL431).