PPT-All-Path Reachability Logic

Andrei Stefanescu 1 Stefan Ciobaca 2 Radu Mereuta 12 Brandon Moore 1 Traian Serbanuta 3 Grigore Rosu 1 1 University of Illinois USA 2 University of Iasi Romania. Please do not alter or modify contents All rights reserved 1FQMFXIFFMMZVDDFGVMJNQMFNFUJHUIJLJMM hy does my child always have an attitude Shes often disruptive disrespectful or picking on other children Shes always the one with a chip on her shoulder Logic. Grigore. . Rosu. and Andrei Stefanescu. University of Illinois, USA. Main Goal. Language-independent. program verification framework. D. erive program properties from . operational semantics. Andrei Stefanescu. 1. , . Stefan Ciobaca. 2. ,. . Radu. Mereuta. 1,2. ,. Brandon Moore. 1. , . Traian. Serbanuta. 3. , . Grigore. Rosu. 1. 1 . University . of Illinois, . USA. 2 . University of Iasi, Romania. Advanced Networking Lab.. Given two IP addresses, the estimation algorithm for the path and latency between them is as follows: Step 1: Map IP addresses to AS numbers. We use BGP routing tables to map an IP address to an AS number. Step 2: Infer AS paths between . t. o Programming Language Semantics,. to Program Verification. Grigore . Rosu. University of Illinois at Urbana-Champaign, USA. 1. How it all started. 1996: Started PhD with Joseph . Goguen. Discovered Maude as “fast OBJ”, then rewriting logic. ?. Anatoliy. . Konversky. ,. academician of National Academy . of Science of Ukraine,. D. ean of Philosophy Faculty. Taras. Shevchenko National University of Kyiv. . Dear colleagues. , participants of the conference! . Grigore . Rosu. , Andrei . Stefanescu. , Brandon Moore. University of Illinois at . Urbana-Champaign, USA. Stefan . Ciobaca. University . Alexadru. . Ioa. n. . Cuza. , Romania. Long-Standing Dream. Logic. Grigore. . Rosu. and Andrei Stefanescu. University of Illinois, USA. Main Goal. Language-independent. program verification framework. D. erive program properties from . operational semantics. . S. . Creese. , M. Goldsmith, J. Nurse, E. Phillips. 11. th. IEEE International Conference on Trust, Security and Privacy in Computing and Communications (. TrustCom. ), 2012,pp. 1124-1131. DOI: 10.1109/. Grigore. . Rosu. University of Illinois at . Urbana-Champaign (UIUC). Joint work with. Chucky Ellison . (UIUC). Wolfram Schulte . (Microsoft Research). How It Started. NASA project runtime . verification effort. We already know that the language of the machine is . binary. – that is, sequences of 1’s and 0’s. But why is this? . At the hardware level, computers are streams of signals. These signals only have two states of interest, high voltage and low voltage. . Logic Gates. NOT (Inverter) Gate. AND Gate. OR Gate. NAND Gate. NOR Gate. XOR Gate. Digital Signals. Digital signals 0 (false) or 1 (true). Digital signal 1 is represented by a small voltage.. Digital signal 0 is represented by no voltage.. Qirun Zhang, Georgia Institute of Technology. Thomas Reps, University of Wisconsin. Outline of Tutorial. CFL-reachability. Origin & background. Algorithm & complexity. Applications. Beyond CFL-reachability. a . Succinct Control Plane Representation . Seyed . K. . Fayaz. Creativity. Once again, . analogy. : . after reading Batfish and HSA: header space .  control space?. Asked Vyas . Sekar. at . Seyed.