PPT-CUDA Performance Considerations

2 of 2 Varun Sampath Original Slides by Patrick Cozzi University of Pennsylvania CIS 565 Spring 2012 Agenda Instruction Optimizations Mixed Instruction Types Loop Unrolling Thread . Basically a child CUDA Kernel can be called from within a parent CUDA kernel and then optionally synchronize on the completion of that child CUDA Kernel The parent CUDA kernel can consume the output produced from the child CUDA Kernel all withou t heterogeneous programming. Katia Oleinik. koleinik@bu.edu. Scientific Computing and Visualization. Boston . University. Architecture. NVIDIA Tesla M2070: . Core clock: 1.15GHz . Single instruction . 448 CUDA cores . . Acknowledgement: the lecture materials are based on the materials in NVIDIA teaching center CUDA course materials, including materials from Wisconsin (. Negrut. ), North Carolina Charlotte (. Wikinson. Getting Righteous Performance from your GPU. Optimizing on CPUs. Could I be getting better performance?. Probably a little . bit, but most of it is hidden from the user.. How . much better?. If you compile –O3, you can get faster (maybe 2x). © Dan Negrut, . 2012. UW-Madison. Dan Negrut. Simulation-Based Engineering Lab. Wisconsin Applied Computing Center. Department of Mechanical Engineering. Department of . Electrical and Computer Engineering. Vinay B Gavirangaswamy. Canny edge detection algorithm. Output. Original. Single Threaded. Output (contd.). Original . Multi-Threaded (. OpenMP. ). Output (contd.). Original. Multi-Threaded. (GPU-CUDA). Hui. Li. Geoffrey Fox. Research Goal. provide . a uniform . MapReduce programming . model that works . on HPC . Clusters or . Virtual Clusters cores . on traditional Intel architecture chip, cores on . HSC PDHPE – CQ2 DP1. What are the planning considerations for improving performance. initial planning considerations. performance and fitness needs (individual, team). schedule of events/competitions. Se-Joon Chung. Background and Key Challenges. The trend in computing hardware is parallel systems.. It is challenging for programmers is to develop applications that transparently scales its parallelism to leverage the increasing number of processor cores.. Ajaya. . Neupane. , . Zhiyun. Qian . and . Nael. Abu-. Ghazaleh. University of California, Riverside. Rendered Insecure: . GPU Side Channel Attacks . are Practical. 1. G. raphics . P. rocessing . Ajaya. . Neupane. , . Zhiyun. Qian . and . Nael. Abu-. Ghazaleh. University of California, Riverside. Rendered Insecure: . GPU Side Channel Attacks . are Practical. 1. G. raphics . P. rocessing . CUDA NEW FEATURES AND UPDATES 2 ANNOUNCING CUDA 10.2 Download today at: https://developer.nvidia.com/cuda - downloads Plus Compiler, Tools and Library Enhancements & Performance Improvements See Relea Cliff Woolley NVIDIADeveloper Technology GroupGPUCPUGPGPU Revolutionizes ComputingLatency Processor Throughput processorLow Latency or High ThroughputCPUOptimized for low-latency access to cached dat May 8-Stephen Jones GTC 2018CUDANEW FEATURESAND BEYOND22CUDA ECOSYSTEM 2018CUDADOWNLOADS IN 20173500000CUDA REGISTERED DEVELOPERS800000GTC ATTENDEES80003CUDA DEVELOPMENT ECOSYSTEMFrom Ease of Use to S