International Journal of Engin ering Trends and Technology IJETT Volume Issue April  ISSN   httpwww

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ijettjournalorg Page 942 Digital IC Testing Using ATE Konijeti Bhavani Satish 1 Kurra Ranjit Kumar 2 Parthiban Selvaraj 3 Pillem Ramesh 4 1 KL University Vaddeswaram Andhra Pradesh India KL University Vaddeswaram Andhra Pradesh India 3 Tessolve serv ID: 36840 Download Pdf

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International Journal of Engin ering Trends and Technology IJETT Volume Issue April ISSN httpwww

ijettjournalorg Page 942 Digital IC Testing Using ATE Konijeti Bhavani Satish 1 Kurra Ranjit Kumar 2 Parthiban Selvaraj 3 Pillem Ramesh 4 1 KL University Vaddeswaram Andhra Pradesh India KL University Vaddeswaram Andhra Pradesh India 3 Tessolve serv

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International Journal of Engin ering Trends and Technology IJETT Volume Issue April ISSN httpwww




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International Journal of Engin ering Trends and Technology (IJETT) Volume Issue April 201 ISSN: 2231 5381 http://www.ijettjournal.org Page 942 Digital IC Testing Using ATE Konijeti Bhavani Satish 1] Kurra Ranjit Kumar [2] Parthiban Selvaraj [3] Pillem Ramesh [4 [1] KL University, Vaddeswaram , Andhra Pradesh, India. KL University, Vaddeswaram, Andhra Pradesh, India. [3] Tessolve services pvt ltd, Bangalore , Karnataka, India [4] KL University, Vaddeswaram, Andhra Pradesh, India. Abstract Automatic Test Equipment ATE ) is any apparatus that performs tests on a device, known as

the Device Under Test (DUT), using automation to quickly perform measurements and evaluate the test resu lts. The IC Testing is done by thorough understanding RIGDWDVKHHWVRIUHVSHFWLYH,&VDQGSURSHUWHVWSODQLVPDGH1RZ the Test plan is executed and the results are noted and are compared with the original values given in the data sheet. The IC (DUT) is tested for different inputs which cover all its functionalities and the respective outputs are noted and compared by the ATE using the given

original IC specifications. The final result of different vectors is shown on the data log by smar test software p UHVHQWLQWKHWHVWFRPSXWHU7KHSDVVHG,&VDUHVHQWWR *RRGELQDQGWKHIDLOHGRQHVDUHVHQWWR%DGELQ Keywords ATE (Automatic Test Equipment), DUT (Device Under Test), ACT (Advanced CMOS Technology). I. INTRODUCTION An ATE is a complicated system containing dozens of complex test instruments (real or simulated

electronic test equipment ) capable of automatically testin g and diagnosing faults in sophisticated electronic packaged parts or on Wafer testing , including System On Chips and Integrated circuits . It gives better way of testing the device compare to bench testing and gives the accurate results. ATE consists of Test head (contains the entire tester electronics) , Manipulator (helps to move the test head in all directions) , Main Frame (gives the mechanical support to the test head and power supply quipment) , cooling unit (helps to keep component of the pin channel at constant temperature

and Test computer (helps to operate the DUT according to given specifications) . The Device Interface Board is designed to fit for the Test Head and the DUT is plac ed on the DIB and the respective tests are performed on the DUT using the Test equipment . There are different types of Test heads in verigy tester namely Small Test Head (STH), Large Test Head (LTH) and Compact Test Head (CTH). The DIB is comp atible for all the test heads of verigy. STH is a 1024 pin Test Head with 4 card cages, LTH is a 20 pin Test Head wit h 8 card cages, and CTH is a 512 pin Test Head with 2 card cages. Each

cage is having 14 slots with 4 DC power supply slots, 1 Device power supply slot, 1 clock board slot and 8 channel board slots. Each channel board serves two pogo blocks and has 32 pins . So one card cage will have 32x8=256 pins. Each slot serves two pogo blocks s1 and s2 where each pogo block is having 16 pin s. S1 is compatible po go block and S 2 is expanded pogo block . Here the main advantage is each pin is programmable i.e., pin scalable. II. GENERAL DESCRIPTION OF IC 74ACT299 The AC/ACT299 is an 8 bit universal shift/storage register with 3 STATE outputs. Four modes of operation are

possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip flops Q0, Q7 to allow easy serial cascad ing. A separate active LOW Master Reset is used to reset the register. III. UNCTIONAL ESCRIPTION OF IC 74ACT299 The AC/ACT299 contains eight edge triggered D type flip flops and the inter stage logic necessary to perform synchronous shift left, shift rig ht, parallel load and hold operations. The type of operation is determined by mode selection

pins S0 and S1. All flip flop outputs are brought out through 3 STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip flops. All other state changes are initiated by the rising edge of the clock. Inputs can chan ge when the clock is in both state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal
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International Journal of Engin ering Trends and Technology (IJETT) Volume Issue April 201 ISSN: 2231 5381 http://www.ijettjournal.org Page 943 on either OE1 or OE2 disables the 3 STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3 STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. TABLE RECOMMENDED OPERATING CONDITI ONS Symbol Parameter Value Unit CC Supply Voltage 4.5 to 5.5 Input Voltage 0 to Vcc Output Voltage 0 to Vcc OP Operating

Temperature 40 to +85 dt/dv Input Rise and Fall Time CC = 4.5 to 5.5 V ns/V IV. TEST ETUP First the user should start the smar test in online mode and a new device is to be created in or der to perform the test on DUT. The initial test setup includes pin configuration, level setup, timing setup and the patterns to be executed and the test flow. It is expl ained as follows: A. Pin configuration It includes the description of the pins and the channel allocation of the pins. The description includes the pin number, pin name, type (i/o/io pin , mode of operation (std and fast) and series

resistance. It can be shown as follows: Fig. Pin configuration definition window shown in the smar test software. B. Grouping of Pins Here the pin groups are def ined based on the common functionality of the pins . This grouping helps us to set the voltage levels, drive points, and receive points at once instead of defining for each pin separately . The grouping is done in the pin configuration windo w itself C. Level Setup 7KLVLVXVHGWRVHWWKHORJLFOHYHOVIRUWKHGLJLWDO,&V7KH logic

levels are IH (high level input voltage), V IL (low level input voltage), V OH (high level output voltage), and V OL (low level output voltage). D. Level equation set It is the e ditor window where the level spec ifications are defined for all the pins. And also the Level set and DPS pins are defined. The following figure shows the respective window. Fig. evel equation set window to define the level equations E. Level Specifications 7KHOHYHOVSHFVFDQEHGHILQHGDWDQRWKHUZLQGRZHGLW

VSHFLILFDWLRQVLQOHYHOVHWXSZLQGRZ Here the variables declared in the level equation set are assigned with respective values.
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International Journal of Engin ering Trends and Technology (IJETT) Volume Issue April 201 ISSN: 2231 5381 http://www.ijettjournal.org Page 944 Fig. 3 evel specifications definition window F. Timing Setup Here the timing is defined i.e. both drive edges and receive edges are defined in the wave table. And the frequency, test er cycle , device cycle, timings of drive e dges and receive edges are defined. These

variables FDQEHGHILQHGLQWKHHGLW VSHFLILFDWLRQVZLQGRZ G. Wave table To define the shape of the input and output (expected) waveform as shown in the following window Fig. 4 Wavetable definition window H. Ti ming Equation set It defines the timings of both drive and receive edges. Here the tester cycle and device cycle are calculated from the frequency. Fig. 5 Timing equation window to define the timing equations. I. iming specifications In timing equation since the defined spec variable is

IUHTXHQF\WKHYDOXHRI the frequency is assigned here in this window Fig. 6 Timing specifications definition window shown in the smar test. J. Patterns It is array of pointers including both inputs and outputs and we define the desired outputs in the patterns and are used to test the DUT. The combinations of inputs and desired outputs are
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International Journal of Engin ering Trends and Technology (IJETT) Volume Issue April 201 ISSN: 2231 5381 http://www.ijettjournal.org Page 945 given to the DUT. Each Vector (pattern) will have its

own number. The following fig ure shows the vectors of shift register (IC 74ACT299) to test all the four modes of operation Fig . 7 Vector definition window shown in the smar test. V. TEST PLAN The Test plan includes th e tests that are to be performed on the DUT. Here the tests that are performed are continuity test, leakage test and functionality test (includes Shift Right, Shi ft Left, Parallel Load data, Hold data and reset operations) . A. Continuity Test It checks the existence of connection from power source to the DUT pin and to the internal diodes. Here the current is forced and

respective vo ltage across the diode is measured. The voltage lies between 0.2 V to 0.7 V generally . The test procedure for continuity test is VHOHFWQHZWHVWIXQFWLRQDQG '&WHVWVDQGFRQWLQXLW\,WKDVWKHIRUFLQJFXUUHQWDQ d voltage limits. After executing the test suite, the result is shown on the UI report. Test suite for continuity Fig. 8 Test suite of ontinuity test. Result of continuity test Fig. 9 Result of ontinuity test shown in the Ui

Report. B. Leakage Test
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International Journal of Engin ering Trends and Technology (IJETT) Volume Issue April 201 ISSN: 2231 5381 http://www.ijettjournal.org Page 946 Here the currents I IL and I IH are measured by forcing the voltages V IL and V IH respectively. The measured currents are compared with the original values and the difference between them is known as leakage current. Similar to continuity test WKHUHLVDOHDNDJHWHVWSUHVHQWLQWKH'& WHVWVDQGWKH respective specifications of

volta ge and current are given and after executing the test suite, the respective results are shown on the UI report. Test suite of leakage test Fig. 10 Test suite of Leakage Test. Result of Leakage Test Fig. 11 Result of Leakeage test shown in the Ui Report. C. Functionality Test Here the IC functionality is tested by giving different vectors and the obtained result is checked with the expected result given in the vector and the result is shown as p ass/fail in the UI report. Result of Functionality Test Fig. 12 Result of Load data Functionality test shown in the Ui Report. VI. TEST FLOW The

series of tests that are to be executed are defined as a test flow. Here it includes continuity, leakage and functionality test suites. Here each individual test suite is assigned with good (pass) and bad (fail) bins. Here all the tests can be executed at once or the individual tests can be executed and the respective results are shown in the UI report. The following figure shows the test flow that is performed on the IC 74ACT299 (Shift Register).
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International Journal of Engin ering Trends and Technology (IJETT) Volume Issue April 201 ISSN: 2231 5381

http://www.ijettjournal.org Page 947 Fig. 13 Test flow showing the series of tests to be executed. VII. RESULT Timing Diagram The Timing Diagram Window helps us to view both actual and expected waveforms so that the actual and expected waveforms can be compared. The Timing Diagram can show both drive and receive edges in the waveform where data is driven and received from DUT. Fig. 14 Timing Diagram displaying the waveforms for Load data functionality. VIII . CONCLUSION The DUT (shift register IC 74ACT299) is tested for Continuity, Leakage and Functionality tests using the Verigy 93k SOC

tester and the respective results are shown above in the pictorial representation. REFERENCES [1] Test concepts and test plan are developed at the Tessolve services pvt ltd, Bangalore. [2] Test results are obtained from the Verigy 93k SOC series ATE done at Tessolve Services Pvt Ltd, Bangalore. [3] Markburns Texas Instruments, Incorporated and Gordon W. Roberts McGill University, An Introduction to mixed signal IC test and measurement, O XFORD UNIVERSITY PRESS, 2001.