PPT-Accelerated Path-Based Timing Analysis with MapReduce

Author : trish-goza | Published Date : 2016-03-04

Tsung Wei Huang and Martin D F Wong Department of Electrical and Computer Engineering ECE University of Illinois at UrbanaChampaign UIUC IL USA 2015 ACM International

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Accelerated Path-Based Timing Analysis with MapReduce: Transcript

Tsung Wei Huang and Martin D F Wong Department of Electrical and Computer Engineering ECE University of Illinois at UrbanaChampaign UIUC IL USA 2015 ACM International Symposium on Physical Design ISPD. Closure. Page . 2. Welcome. This module will help you understand how your synthesis tool, the ISE software, HDL coding style, and other factors that affect your ability to meet your system timing objectives. Session at . Silicon India. Rajgopal Kishore. Vice President and Global Head of BI & Analytics, . HCL Technologies. rkishore@hcl.in. rkishore9@gmail.com. . State of data. Challenges. Need of the day. Subramanyam. Sripada. Synopsys . Inc. 3/13/2015. Constraint Analysis/Debug/Management. Budgeting Issues. Functional. Scan. Test. Low_Power. More Modes. More Files/. More complex. constraints. IP Blocks. Subramanyam Sripada. Murthy Palla. Synopsys Inc.. March 12, 2013. Agenda. Motivation. Background. Approach. Illustration of Approach. Results. Design/Complexity Projections. An idea of what you can expect. PrimeTime. . Speaker: Bob Tsai. Advisor: . Jie. -Hong Roland Jiang . Introduction. Flow. On Chip Variation (OCV). Manual/automated . netlist. editing. Signal integrity and crosstalk. Outline. PrimeTime. Recovery . With . Flexible . Flip-Flop Timing . Model. Andrew B. Kahng and . Hyein Lee. UC . San . Diego VLSI CAD Laboratory. Outline. Preliminary. Motivation. Related Work. Sequential LP-based Optimization. Objectives. After completing this module, you will be able to:. Describe a flow for obtaining timing closure. Interpret a timing report and determine the cause of timing errors. Apply Timing Analyzer report options to create customized timing reports. Qiuyang Wu. 2015.3.13. Outline. This talk answers the following questions regarding timing constraints:. What are the key scalability challenges?. What are the available solutions?. Design Complexity Trends. Static Timing Analysis. Tom Spyrou . TAU 2013. 3/2013. Goal of this talk. Higher level than latest trends. Remind ourselves the trade-offs we have made as an industry to have a workable solution for STA. in a Mixed Signal World. TAU Workshop Panel Session. Jim Sproch. March 12, 2015. Are Existing Delay Models Useful for. Mixed Signal Timing Analysis?. Mixed signal designs comprise a mix of digital, analog, and analog-ish circuits. Tsung. -Wei Huang. and Martin D. F. Wong. Department of Electrical and Computer Engineering (ECE). University of Illinois at Urbana-Champaign (UIUC), IL, USA. 2015 ACM International Symposium on Physical Design (ISPD). Andrew B. Kahng. +$. , . Uday Mallappa. $. . and . Lawrence Saul. +. UC San Diego . $. ECE & . +. CSE Department. Preliminaries . Modeling Features. Modeling Methodology. Experiments . Conclusions. With . Flexible . Flip-Flop Timing . Model. Andrew B. Kahng and . Hyein Lee. UC . San . Diego VLSI CAD Laboratory. Outline. Preliminary. Motivation. Related Work. Sequential LP-based Optimization. Experimental Results. Boshen. Jiao, PhD, MPH. Harvard T.H. Chan School of Public Health. Acknowledgement. Collaborators. Stéphane . Verguet. , PhD, MPP (Harvard). Yuli. (Lily) Hsieh, MPH (Harvard). Disclosure. No funding support and conflict of interest related to this study.

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