Automating Builds with Makefiles - PowerPoint Presentation

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Automating Builds with Makefiles

C Programming in a Linux Environment

Compiling Your Program

coord.c:

#include<stdio.h>

double getDouble(char [], double, double);double dist(double x, double y);int main() { // Read the (x, y) coordinates of a 2D point // where each coordinate is in [-10, 10] // and compute the distance of (x, y) // from the origin. double x = getDouble("Enter the x value: ", -10, 10); double y = getDouble("Enter the y value: ", -10, 10); double distance = dist(x, y); printf("Distance from origin is %.2lf\n", distance);}

helper.c: #include<stdio.h>#include<math.h>double dist(double x, double y) { double d = sqrt(pow(x, 2) + pow(y, 2)); return d;}double getDouble(char prompt[], double min, double max) { double readValue; do{ printf("%s", prompt); scanf("%lf", &readValue); if(readValue < min) printf("Value must be >= %lf\n", min); if(readValue > max) printf("Value must be <= %lf\n", max); } while(readValue < min || readValue > max); return readValue;}

Compile and run: % c99 coord.c helper.c -o coord -lm OR % c99 coord.c helper.c -lm% ./coord % ./a.out

-lm



link with math library

C compilation

gcc

-

std=c99 <sourcefile>.c Flags:-g: include debugging info-o <output>: specifies the name of the output filegcc –std=c99 prog.c –o progExecutable is prog, not a.out, so to run program: ./prog-c: build the object file (produces .o file)

Separate Compilation

% gcc

–

c helper.c % gcc –c coord.cNow link:% gcc –o coord helper.o coord.o –lmNote that the executable is coord. To run:% ./coord

We will automate the build with a makefile.Compile separately.If one file changes, only recompile that one.link with math library

make Utility & Makefiles

Unix tool

make

- used to simplify compilationmakefile: a text file that contains recipes for building your executable file. Carry out the build by typing make on the command lineFor each target (object files, executable) you want to build, include:dependencies: if these files change, you will need to re-build the targetcommand: command to carry out to build the targetmake will only re-build a target if the dependencies have been modified. Format: target: [dependencies]<tab> <command>

makefile for coord

# This is a comment. File name is makefile

# The

first target in file is the one that is built when you type "make"# To build a different target, type "make <target>"# There must be a tab at the beginning of the command lines.coord: coord.o helper.o gcc –o coord coord.o helper.ocoord.o: coord.c gcc –c coord.chelper.o: helper.c

gcc –c helper.c

Using the makefile

If I edit helper.c, and then type:

% make

gcc -c helper.cgcc -o coord coord.o helper.o -lm% ./coordEnter the x value: 3Enter the y value: 4Distance from origin is 5.00These are the commands in makefile that had to be executed since helper.c changed.Execute

user input is underlined

Source in Separate Files

readDouble.c

double getDouble(char prompt[], double min, double max) {

double readValue; do{ printf("%s", prompt); scanf("%lf", &readValue); if(readValue < min) printf("Value must be >= %lf\n", min); if(readValue > max) printf("Value must be <= %lf\n", max); } while(readValue < min || readValue > max); return readValue;}noNeg.cint main() { // read a non-neg double, and then // compute and return its square root. double val = getDouble("Enter a non-neg #: ", 0, 100); return sqrt(val);}

Simple Example

file1.c

file2.c

file1.h#include "file1.h"int main() { // Call function in file2.c file2Function();}#include<stdio.h>#include "file1.h"void file2Function() { printf("Makefiles FTW");}// Example include filevoid file2Function(); To compile and run:gcc –o file1 file1.c file2.c OR gcc file1.c file2.c./file1 ./a.outProblem: If we have large .c files and change one, then we want to only recompile the one that changed, and link the .o files to get executable.

Exercise

So let's produce the object files from the .c files separately, and then link them, so that changes in one won't force us to recompile both:

gcc

–c file1.cgcc –c file2.c Write a makefile that contains 3 targets: file1 (the executable), file1.o and file2.o. Note that a change in the file1.h will affect file1.o and file2.o.