Performance Analysis And Acceleration of High

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Performance Analysis And Acceleration of High Bandwidth Memory System Rohit Devidas Chavan, Jyoti Verma, Sekhar Dangudubiyyam 1 Accellera Systems Initiative 2 AGENDA Objective HBM3 Subsystem Architecture Performance Analysis for HBM3

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Performance Analysis And Acceleration of High Bandwidth Memory System Rohit Devidas Chavan, Jyoti Verma, Sekhar Dangudubiyyam 1

© Accellera Systems Initiative 2 AGENDA Objective
HBM3 Subsystem Architecture
Performance Analysis for HBM3
Protocol Analysis for HBM3
Target Metric Numbers
Results and Key Takeaways
Future Work Identified for the Methodology

© Accellera Systems Initiative 4 HBM3 Sub-System Architecture Subsystem consists of 16 channels.
We have used AXI-4 VIPs to generate data traffic.
DFI Monitor has been integrated to monitor DFI interface.
HBM3 memory model has been used with different density and stack configurations.
Three different frequencies are tested which are 4800MHz, 5600MHz and 6400MHz.

© Accellera Systems Initiative 6 Metric View Single Value Metrics Available Metrics Selected HBM3 Channel Instance The improved performance of our subsystem was achieved due to fast analysis with protocol analyzer.
Protocol analyzer helped us fine tune our scenarios w.r.t. address mapping and data traffic.
After using directed addresses to different row, column, bank and bank groups, the performance increased significantly.

© Accellera Systems Initiative 7 Parameter Graphical View The graph represents the delay between activate to write command to a bank.

This graph also gives us the time instances where violations have occurred. Multi Value Instance Metrics Metric Result Details Parameter Violation

© Accellera Systems Initiative 10 Protocol Analyzer View This view consists of protocol analyzer window, nWave window, and details of a transaction.

All the shown windows are time synchronized. Protocol Analysis Waveform Analysis Command Details

Performance Analysis And Acceleration of High

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