MONOSTABL MULTIVIBRATO Single Retriggerable A B B CL Q TO VIE Thi i a monostabl multivibrato o puls generator Th circui mus triggered respons t a trigger th Q outpu goe hig an th Q outpu goe low sta
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MONOSTABL MULTIVIBRATO Single Retriggerable A B B CL Q TO VIE Thi i a monostabl multivibrato o puls generator Th circui mus triggered respons t a trigger th Q outpu goe hig an th Q outpu goe low sta

Certai form o clipo digita tester ca upse th operatio o thi stage particularl o th resisto an capacito inputs Unles ver shor time o complementar output o retriggerabilit needed th 555 i a bette choic o monostabl multivibrator Curren pe packag 2 mill

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MONOSTABL MULTIVIBRATO Single Retriggerable A B B CL Q TO VIE Thi i a monostabl multivibrato o puls generator Th circui mus triggered respons t a trigger th Q outpu goe hig an th Q outpu goe low sta




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Presentation on theme: "MONOSTABL MULTIVIBRATO Single Retriggerable A B B CL Q TO VIE Thi i a monostabl multivibrato o puls generator Th circui mus triggered respons t a trigger th Q outpu goe hig an th Q outpu goe low sta"— Presentation transcript:


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7412 MONOSTABL MULTIVIBRATO (Single Retriggerable A B B CL Q TO VIE Thi i a monostabl multivibrato o puls generator Th circui mus triggered respons t a trigger th Q outpu goe hig an th Q outpu goe low stayin ther fo a predetermine tim an the returnin th initia state capacito connecte betwee pin 1 an 1 determine th puls widt i combinatio wit a resisto betwee pi 1 an pi 14 Fig 4-3 give th time-constan curves Th resisto ca rang fro 5 25 an th capacito fro 1 p upward Ther ar severa way t trigge th monostabl multivibrator de termine b wha yo d t th Al A2 Bl B2 an Clea inputs Al A2

an B ar high a low-to-hig transitio o B triggers Al Bl an B ar high a high-to-lo transitio o A triggers Th Clea inpu shoul remai high I grounded i mhibit trigger in an return th circui t th stat wit Q lo an Q high Th circui ma b retriggere a an time B sure to properly ter- minate oil four trigger inputs. Certai form o clip-o digita tester ca upse th operatio o thi stage particularl o th resisto an capacito inputs Unles ver shor time o complementar output o retriggerabilit needed th 555 i a bette choic o monostabl multivibrator Curren pe packag 2 milliampere typica
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7412

MONOSTABL MULTIVIBRATO (Dual Retriggerable TO VIE Thi I a dua monostabl multivibrato o puls generator Eac hal o th circui mus b triggered Eac hal o th circui ma b use separately respons t a trigger th Q outpu goe hig an th Q outpu goe low stayin ther fo a predetermine tim an the returnin th initia state capacito an resisto connecte a show determin th puls width Fig 4-3 give th time-constan curves Th resisto ca rang fro 5 t 25 an th capacito fro 1 p upward Ther ar tw way t trigge th monostabl multivibrator I inpu i hel /ow bringin B fro lo t hig triggers I inpu B i hel high, bringin inpu A fro

hig t lo triggers Th Clea inpu shoul remai high I grounded i inhibit triggerin an return th circui t th stat wit Q lo an Q high Th circui ma b retriggere a an time B sure to properly fer minote all Trigger and Clear inputs. Certai form o clip-o digita tester ca upse th operatio o thi stage particularl o th Resisto an Capacito inputs Unles ver shor time o complementar output o retriggerabilit needed th 555 i a bette choic o monostabl multivibrator Curren pe packag 4 milliampere typica
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tor mus b use i thi circuit Th temperatur rang i fro -30 +50° wit th prob shown Th resolutio i

0. degree NEGATIVE-RECOVER CIRCUIT Ordinar monostabl circuit nee a certai tim t recove afte triggering I th recover tim i no completed th nex tim cycl OUTPU PULS WIDT VERSU TIMIN RESISTO m n 7 1 2 Ry-TIMIN RESISTOR-K 9+5 4nT4l OUTPU ^- 1 7412 INPU TRIGGE OUTPU si +5 GN (A 74121 Fig 4-30 Monostabl circuit
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migh b shortened an a inaccurac o jitte ca result A a gen era rule monostabl circuit operat bes i th recover tim exceed th O time althoug yo ca operat wit O time o 90 i yo are carefu an choos th righ resisto values Som specia circuit le u retrigge th monostabl circui a an time

Thes ar calle negative-recovery monostable circuits. The ar use fo missing-puls detection voice-controlle systems cod anal 1000 700 400 200 100 70 40 20 10 •iMirwiliiiiiifiiiwiimmiMMn - OUTPU PULS WIDT TIMIN CAPACITANC - 2 4 7 1 2 4 7 10 20 40 70 100 C^ --TIMIN CAPACITANC - p +5 2,3,4 5 C +5 TRIG "I -o OUTPU -o 1 +5V( 7412 (DUAL 7412 10 i -o INPU TRIGGE o +5 GN J OUTPU «i I -o "IT TRI 2 +5 o WJH C (C 74123 (B 74122 usin th 74121 74122 an 74123
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TYPE SN5446 W '48 '49 SN54L46 'L47 SN54LS47 'LS48 LS49 TYPE SNS'l'bA ^ ^0 , ,^^ SN74LS47 1348 134 3N744BA '"JJP'^^OIEVE 3EGIV1EN

DEC0DER3/DRIVER iiiiMiiiiiiiiiJ iiMlTWIITMIMIIBillilllll 1 ' ii*"i"i'"'W'«'"aa'MM'i^MM^""''"'*^^^^^^^™"*M"M* '49 'LS4 featur Open-Collecto Output Blankin Inpu '48 'LS4 featur Interna Pull-Up Eliminat Nee fo Externa Resistor Lamp-Tes Provisio Leading/Trailin Zer Suppressio '46A '47A X46 'L47 TS4 featur Open-Collecto Output Driv Indicator Directl Lamp-Tes Provisio Leading/Trailin Zer Suppressio Al Circui Type Featur Lam Intensit Modulatio Capabilit TYPICA POWE DISSIPATIO 32 m 32 m 26 m 16 m 16 m 16 m m 12 m m 32 m 32 m 26 m 16 m 16 m m 12 m m PACKAGE MA VOLTAG OUTPU CONFIGURATIO open-collecto

open-collecto 2-k pull-u open-collecto open-co lecto open-c I lecto open-collecto 2-k pull-u open-collecto open-collecto open-collecto 2-k pull-u open-collecto open-collecto open-collecto 2-kl pull-u open-collecto TYP SN5446 SN5447 SN544 SN544 SN54L4 SN54L4 SN54LS4 SN54LS4 SN54LS4 SN7446 SN7447 SN744 SN74L4 SN74L4 SN74LS4 SN74LS4 SN74LS4 ACTIV LEVE lo lo hig hig lo lo lo hig hig lo lo hig lo lo lo hig hig '49 'LS4 (TO VIEW '48 'LS4 (TO VIEW '46A '47A 'L46 'L47 'LS4 (TO VIEW OUTPUT OUTPUT vc ^ [laJTLMJTLrr H [^UlTljriJaUT ft4iL[tuti|kjiHjjn4yu Vc Jls ^^E abe g a b C LTRBORB D A Bl C LTRBORB D A

m±i msj 'Hminireninpi .—1 TES OUT IN ^ s " .MOXT PU PU INPUT nimruriinArti y U INPUT INPUTS LAM R R TES OUT IN positiv logic se functio table
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TYPE SN5446A '47A 48 49 SN54L46 147 SN54LS47 'LS48 'LS49 SN7446A '47A 48 SN74L46 147 SN74LS47 1S48 LS4 BCD-TO-SEVEN-SEGMEN DECODERS/DRIVER descriptio Th '46A 'L46 '47A 'L47 an 'LS4 featur active-lo output designe fo drivin common-anod VLED o incandescen indicator directly an th '48 '49 'LS48 'LS4 featur active-hig output fo drivin lam buffer o common-cathod VLEDs Al o th circuit excep '4 an 'LS4 hav ful ripple-blankin input/outpu control

an a lam tes input Th '4 an 'LS4 circuit incorporat a direc blankin input Segmen identificatio an resultan display ar show below Displa pattern fo BC inpu count abov 9 ar uniqu symbol t authenticat inpu conditions Th '46A '47A '48 'L46 ''L47 'LS47 an 'LS4 circuit incorporat automati leadin and/o trailing-edg zero-blankin contro (RB an RBO) Lam tes (LT o thes type ma b performe a an tim whe th BI/RB nod i a a hig level Al type (includin th '4 an 'LS49 contai a overridin blankin inpu (Bl whic ca b use t contro th lam intensit b pulsin o t inhibi th outputs Input an output ar entirel compatibl fo

us wit TT o DT logi outputs Th SN54246/SN7424 throug '24 an th SN54LS247/SN74LS24 throug 'Lsl4 compos th fil an th 9 wit tail an hav bee designe t offe th designe a choic betwee tw indicato fonts Th SN54249/SN7424 an SN54LS249/SN74LS24 ar 16-pi version o th 14-pi SN544 an 'LS49 Include i th '24 circui an 'LS24 circuit ar th ful functiona capabilit fo lam tes an rippl blanking whic i no availabl i th '4 o 'LS4 circuit IZI IZ 3 4 5 6 7 8 9 1 1 1 1 MUMERICA DESIGNATION AN RESULTAN DISPLAY SEGMEN IDENTIFICATIO DECIMA FUNCTIO RB '46A/47A/L46, INPUT RB C B A L L L L L H L H L L H H H L L H L H H H L

H H H L L L L L H L H L L H H H L L H L H H H L H H H X X X L L L X X X L47 'LS4 FUNCTIO TABL BI/RBO OUTPUT OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF NOT = hig level L = lo level X = irrelevan NOTES 1 Th blankin inpu (Bl mus b ope o hel a a hig logi leve whe outpu function 0 throug 1 ar desired Th ripple-blankin inpu (RBI mus b ope o hig i blankin o a decima zer i no desired Whe a lo logi leve i applie directl t th blankin inpu (Bl) al segmen output ar

of regardles o th leve o an othe input Whe ripple-blankin inpu (RBI an input A B C an D ar a a lo leve wit th lam tes inpu high al segmen output of an th ripple-blankin outpu (RBO goe t a lo leve (respons condition) Whe th blankin input/rippl blankin outpu (BI/RBO i ope o hel hig an a lo i applie t th lamp-tes input al segmen output ar on BI/RB i wire-AN logi servin a blankin inpu (Bl and/o ripple-blankin outpu (RBO)
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TYPE SN54192 SN54193 SN54L192 SN54L193 SN54LS192 SN54LS19 SN74192 SN74193 SN74L192 SN74U93 SN74LS192 SN74LS19 SYNCHRONOU 4-BI UP/DOW COUNTER (OUA CLOC WIT CLEAR

BULLETI NO DL- 77 1828 DECEMBE 1972-REVISE AUGUS I97 SN54' SN54LS' . J O W PACKAG SN54L'... PACKAG SN74' SN74L' SN74LS'.. J O N PACKAG (TO VIEW Cascadin Circuitr Provide Internall Synchronou Operatio Individua Prese t Eac Flip-Flo Full Independen Clea Inpu OUTPUT A 'nATAPifA A 'inA HA A HATA TYPICA MAXIMU TYPICA COUN FREOUENC POWE DISSIPATIO '192/19 3 MH 32 m 'L192/L19 7 MH 4 m 'LS192/LS19 3 MH 9 m descriptio Thes monolithi circuit ar synchronou reversibl (up/down counter havin a complexit o 5 equivalen gates Th '192 'L192 an 'LS19 circuit ar BC counter an th '193 'L19 an 'LSI9 ar 4-bi binar

counters Synchronou opera tio i provide b havin al flip-flop clocke simultaneousl s tha th output chang coinci dentl wit eac othe whe s instructe b th steerin logic Thi mod o operatio eliminate th outpu countin spike whic ar normall associate wit asynchronou (ripple-clock counters Th output o th fou master-slav flip-flop ar triggere b a low-to-high-leve transitio o eithe coun (clock input Th directio o countin i determine b whic coun inpu i pulse whil th othe coun inpu i high Al fou counter ar full programmable tha is eac outpu ma b prese t eithe leve b enterin th desire dat th dat input whil

th loa inpu i low Th outpu wil chang t agre wit th dat input independentl o th coun pulses Thi featur allow th counter t b use a modulo- divider b simpl modifyin th coun lengt wit th prese inputs clea inpu ha bee provide whic force al output t th lo leve whe a hig leve i applied Th dea functio independen o th coun an loa inputs Th clear count an loa input ar buffere t lowe th driv require ments Thi reduce th numbe o cloc drivers etc. require fo lon words Thes counter wer designe t b cascade withou th nee fo externa circuitry Bot borro an carr output ar availabl t cascad bot th up an

down-countin functions Th borro outpu produce a puls equa i widt th count-dow inpu whe th counte underflows Similarly th carr outpu produce a puls equa i widt t th count-u inpu whe a overflo conditio exists Th counter ca the b easil cascade b feedin th borro an carr output t th count-dow an count-u input respectivel o th succeedin counter TYPE CLEA BORRO CARR LOA C COUN COUN ° °^ ^ Q Q iinjjiiJiiJLiji±imi± DAT O 0 COUN COUN O O GN 'NPU OUTPUT logic Lo inpu t loa set Q = A = B.Q = C,andO = D absolut maximu rating ove operatin free-ai temperatur rang (unles otherwis noted Suppl voltage Vc (se

Not 1 Inpu voltag Operatin free-ai temperatur rang Storag temperatur rang SN54 5. SN54L 5. SN54LS -5 t 12 -6 t 15 SN74 5. SN74L 5. SN74LS 0to7 -6 t 15 UNI NOT 1 Voltag value ar wit respec t networ groun terminal