NJIT ECE271 Dr. Serhiy - PowerPoint Presentation

NJIT ECE271 Dr. Serhiy Levkov Chap 4-1 Topic 4Field-Effect Transistors ECE 271 Electronic Circuits I

NJIT ECE271 Dr. Serhiy LevkovChap 4- 2 Chapter GoalsDescribe structure and operation of MOSFETs. Define FET characteristics in operation regions of cutoff, triode and saturation. Develop mathematical models for i -v characteristics of MOSFETs. Introduce graphical representations for output and transfer characteristic descriptions of electron devices. Define and contrast characteristics of enhancement-mode and depletion-mode FETs. Define symbols to represent FETs in circuit schematics. Investigate circuits that bias transistors into different operating regions. Explore FET modeling in SPICE.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 3 Intro (1)Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices:

NJIT ECE271 Dr. Serhiy LevkovChap 4- 4 Intro (1)Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 5 Intro (1)Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 6 Intro (1)Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) There are two basic types of solid state transistors: BJT (bipolar junction transistor) and FET (field effect transistor).

NJIT ECE271 Dr. Serhiy LevkovChap 4- 7 Intro (1)Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) There are two basic types of solid state transistors: BJT (bipolar junction transistor) and FET (field effect transistor). FET: electric field is used to control the shape and the conductivity of the channel of one type charge carrier ( p or n ) in semiconductor device. They are also called unipolar to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT).

NJIT ECE271 Dr. Serhiy LevkovChap 4- 8 Intro (1)Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) There are two basic types of solid state transistors BJT (bipolar junction transistor) and FET (field effect transistor). FET: electric filed is used to control the shape and hence the conductivity of the channel of one type charge carrier ( p or n ) in semiconductor device. They are also called unipolar to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT). FET can be of two major types MOSFET (metal oxide semiconductor field effect transistor (mostly used)), and JFET (junction field effect transistor).

NJIT ECE271 Dr. Serhiy LevkovChap 4- 9 Intro (2)Metal Oxide Semiconductor Field Effect device was first solid state device conceived ( Lilienfield , 1928), however it took very long to develop a successful commercial application of such devices. The first successful device was fabricated in 1950, however the reliable commercial fabrication did not start until decade later. Today, the CMOS technology based on MOSFET is the dominant technology in electronics.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 10 Intro (2)Metal Oxide Semiconductor Field Effect device was first solid state device conceived (Lilienfield, 1928), however it took very long to develop a successful commercial application of such devices. The first successful device was fabricated in 1950, however the reliable commercial fabrication did not start until decade later. Today, the CMOS technology based on MOSFET is the dominant technology in electronics. BJT devices were first introduced in 1948 and quickly became commercially available. The first IC with logic gates and operational amplifiers that appeared in early 1960s, were based on BJT technology. They are still widely used, particularly in applications requiring high speed and high precision. BJT device is based on pn -junction structure, while MOSFET is utilizing the MOS capacitor structure.

NJIT ECE271 Dr. Serhiy LevkovMetal Oxide Semiconductor Field-Effect Transistors (MOSFET) Chap 4- 11

NJIT ECE271 Dr. Serhiy LevkovChap 4- 12 MOS Capacitor StructureMetal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 13 MOS Capacitor StructureMetal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 14 MOS Capacitor StructureMetal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 15 MOS Capacitor StructureMetal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate .

NJIT ECE271 Dr. Serhiy LevkovChap 4- 16 MOS Capacitor StructureMetal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. Second electrode (Substrate, Body): n - or p -type semiconductor.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 17 MOS Capacitor StructureMetal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. Second electrode (Substrate, Body): n - or p -type semiconductor. The semiconductor body has limited supply of holes and electrons, and substantial resistivity.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 18 MOS Capacitor StructureMetal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. Second electrode (Substrate, Body): n - or p -type semiconductor. The semiconductor body has limited supply of holes and electrons, and substantial resistivity. The concentration of carriers being dependant on voltage, the capacitance of this structure therefore is a nonlinear function of voltage applied.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 19 Substrate Conditions for Different BiasesAccumulation : V G <<V TN The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor) We consider the conditions of the semiconductor region ( p -type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion. Those conditions are determined by V TN (0.5 - 2.0 V) the threshold voltage, at which the electron inversion layer is just starting to form.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 20 Substrate Conditions for Different BiasesAccumulation : V G <<V TN , V G < 0 The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor) Depletion: 0< V G <V TN The small positive charge of the gate wipe out the holes from the layer below (depletes free carriers) creative a negative charge of ionized atoms We consider the conditions of the semiconductor region ( p -type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion. Those conditions are determined by V TN (0.5 - 2.0 V) the threshold voltage, at which the electron inversion layer is just starting to form.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 21 Substrate Conditions for Different BiasesAccumulation : V G <<V TN The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor) Depletion: 0< V G <V TN The small positive charge of the gate wipe out the holes from the layer below (depletes free carriers) creative a negative charge of ionized atoms Inversion: V G >V TN The larger positive charge of the gate attracts electrons whose concentration in the very thin layer exceeds that of holes – inversion of p-type into n-type. We consider the conditions of the semiconductor region ( p -type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion. Those conditions are determined by V TN (0.5 - 2.0 V) the threshold voltage, at which the electron inversion layer is just starting to form.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 22 Low-frequency C-V Characteristics for MOS Capacitor on P-type SubstrateMOS capacitance is non-linear function of voltage. Total capacitance in any region is dictated by the separation between capacitor plates. Total capacitance can be modeled as series combination of fixed oxide capacitance and voltage-dependent depletion layer capacitance.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 23 NMOS Transistor: Structure A N-MOSFET is formed by adding two heavily doped n -type ( n + , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 24 NMOS Transistor: Structure4 device terminals: Gate(G) A N-MOSFET is formed by adding two heavily doped n -type ( n + , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 25 NMOS Transistor: Structure4 device terminals: Gate(G) Drain(D) A N-MOSFET is formed by adding two heavily doped n -type ( n + , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 26 NMOS Transistor: Structure4 device terminals: Gate(G) Drain(D), Source(S) A N-MOSFET is formed by adding two heavily doped n -type ( n + , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 27 NMOS Transistor: Structure4 device terminals: Gate(G) Drain(D), Source(S) Body(B) A N-MOSFET is formed by adding two heavily doped n -type ( n + , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 28 NMOS Transistor: Structure4 device terminals: Gate(G) Drain(D), Source(S) Body(B). Source and drain regions form pn junctions with substrate. A N-MOSFET is formed by adding two heavily doped n -type ( n + , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 29 NMOS Transistor: Structure4 device terminals: Gate(G) Drain(D), Source(S) Body(B). Source and drain regions form pn junctions with substrate. v SB ,= v S – v B , v DS = v D - v S and v GS = v G - v S are typically nonnegative during normal operation. A N-MOSFET is formed by adding two heavily doped n -type ( n + , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 30 NMOS Transistor: Structure4 device terminals: Gate(G) Drain(D), Source(S) Body(B). Source and drain regions form pn junctions with substrate. v SB ,= v S – v B , v DS = v D - v S and v GS = v G - v S are always positive during normal operation. v B <= v D and v B <= v S , to keep pn junctions reverse biased. A N-MOSFET is formed by adding two heavily doped n -type ( n + , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 31 NMOS Transistor and Variable ResistorA transistor is a three (or four) terminal device, in which one terminal controls the voltage or current between other two terminals In certain way it is similar to a variable resistor, in which the movement of the middle terminal controls the voltage. + - + -

NJIT ECE271 Dr. Serhiy LevkovChap 4- 32 NMOS Transistor: Qualitative Behavior @ vDS =0 V GS <<V TN ( V GS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 33 NMOS Transistor: Qualitative Behavior @ vDS =0 V GS <<V TN ( V GS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows. V GS <V TN ( V GS >0): Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 34 NMOS Transistor: Qualitative Behavior @ vDS =0 V GS <<V TN ( V GS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows. V GS <V TN ( V GS >0): Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. V GS >V TN : Channel is formed between source and drain by electrons in inversion layer . If V DS >0, finite i D flows from drain to source. i B =0 and i G =0.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 35 Since the induced inversion layer is formed by electrons, it’s called N-channel MOSFET. NMOS Transistor: Qualitative Behavior @ v DS =0

NJIT ECE271 Dr. Serhiy Levkov Chap 4- 36 NMOS Transistor: Triode Region where K n = K n ’W /L – the gain factor K n ’= m n C ox ’’ (A/V 2 ) C ox ’’=  ox / T ox  ox = oxide permittivity (F/cm) T ox = oxide thickness (cm ) for Applying a small v DS creates a flow of electrons in the induced inversion layer between source and drain - current i D ( i D = i S , since i B = 0 and i G = 0) . This is the triode region ( linear region, ohmic mode).   MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages .

NJIT ECE271 Dr. Serhiy LevkovChap 4- 37 N-MOS Transistor: Triode Region(derivation of the source-drain current) Since currents i B and i G both are zero, and there is no path for drain current to escape: i S = i D . To find it, we consider the transport of the charge. The linear density of the electron charge at any point in the channel is: The voltage v ox is the function of position x in the channel : . For inversion layer to exist, should be v ox > V TN , so Q’ = 0 until v ox > V TN . At the source, v ox = v GS and it decrease to v ox = v GS - v DS at the drain. The electron drift current is : , where Combining everything: and integrating: , we get

NJIT ECE271 Dr. Serhiy LevkovChap 4- 38 Triode (a bit of history) A  triode  is an electronic amplification device having three active electrodes. most commonly it’s a vacuum tube with three elements: the filament (cathode), the  grid (controlling element), and the plate or anode. The triode vacuum tube was the first electronic amplification device . It’s iv- characteristics was quite linear.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 39 N-MOSFET: Triode Region Characteristics The expression for i D is quadratic in v DS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 40 N-MOSFET: Triode Region Characteristics The expression for i D is quadratic in v DS with max reached at v DS = v GS - v TN = v OV v DS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 41 N-MOSFET: Triode Region Characteristics The expression for i D is quadratic in v DS with max reached at v DS = v GS - v TN = v OV F or small v DS << v GS - v TN , the characteristics i D vs. v DS appear to be linear (triode region, linear) v DS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 42 N-MOSFET: Triode Region CharacteristicsUnder this condition, MOSFET behaves like a gate-source voltage - controlled resistor between source and drain, The expression for i D is quadratic in v DS with max reached at v DS = v GS - v TN = v OV F or small v DS << v GS - v TN , the characteristics i D vs. v DS appear to be linear (triode region, linear)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 43 N-MOSFET: Triode Region Characteristics Under this condition, MOSFET behaves like a gate-source voltage - controlled resistor between source and drain, where on-resistance : The expression for i D is quadratic in v DS with max reached at v DS = v GS - v TN = v OV F or small v DS << v GS - v TN , the characteristics i D vs. v DS appear to be linear (triode region, linear)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 44 MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator

NJIT ECE271 Dr. Serhiy LevkovChap 4- 45 MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator

NJIT ECE271 Dr. Serhiy LevkovChap 4- 46 MOSFET as Voltage-Controlled Resistor Example: Voltage-Controlled Attenuator

NJIT ECE271 Dr. Serhiy LevkovChap 4- 47 MOSFET as Voltage-Controlled ResistorExample: Voltage-Controlled Attenuator If K n =500 m A/V 2 , V TN =1V, R =2k  and V GS = 1, 1.5, 2 V:

NJIT ECE271 Dr. Serhiy LevkovChap 4- 48 MOSFET as Voltage-Controlled ResistorExample: Voltage-Controlled Attenuator If K n =500 m A/V 2 , V TN =1V, R =2k  and V GS = 1, 1.5, 2 V:

NJIT ECE271 Dr. Serhiy LevkovChap 4- 49 MOSFET as Voltage-Controlled ResistorExample: Voltage-Controlled Attenuator If K n =500 m A/V 2 , V TN =1V, R =2k  and V GS = 1, 1.5, 2 V:

NJIT ECE271 Dr. Serhiy LevkovChap 4- 50 MOSFET as Voltage-Controlled ResistorExample: Voltage-Controlled Attenuator To maintain triode region operation, or If K n =500 m A/V 2 , V TN =1V, R =2k  and V GS = 1, 1.5, 2 V:

NJIT ECE271 Dr. Serhiy Levkov Chap 4- 51 NMOS Transistor: inversion layer change V OV - overdrive voltage If we increase v DS , and it’s no more v DS << V GS - V TN = V OV (triode region limit), it starts influencing the depth of induced inversion layer, for which we need V GS > V TN.

NJIT ECE271 Dr. Serhiy Levkov Chap 4- 52 NMOS Transistor: inversion layer change If we increase v DS , and it’s no more v DS << V GS - V TN = V OV (triode region limit), it starts influencing the depth of induced inversion layer, for which we need V GS > V TN. v DS = V OV - pinch-off voltage, saturation region begins V OV - overdrive voltage

NJIT ECE271 Dr. Serhiy Levkov Chap 4-53 NMOS Transistor: Saturation Region is also called saturation or pinch-off voltage . What is the current in saturation region? When v DS increases above triode region limit, channel region akmost disappears, MOSFET also said to be pinched-off. Current saturates at (almost) constant value, independent of v DS .

NJIT ECE271 Dr. Serhiy Levkov Chap 4- 54 NMOS Transistor: Saturation Region Substituting v DS = v GS - V TN into previous equation for drain current, we get Example here Saturation region operation mostly used for analog amplification. is also called saturation or pinch-off voltage . When v DS increases above triode region limit, channel region akmost disappears, MOSFET also said to be pinched-off. Current saturates at (almost) constant value, independent of v DS .

NJIT ECE271 Dr. Serhiy LevkovChap 4- 55 NMOS Transistor: iv-characteristic

NJIT ECE271 Dr. Serhiy LevkovChap 4- 56 NMOS Transistor: Region SummaryIf v DS << V GS - V TN MOSFET is in linear portion of the triode region Triode

NJIT ECE271 Dr. Serhiy LevkovChap 4- 57 NMOS Transistor: Region SummaryIf v DS << V GS - V TN MOSFET is in linear portion of the triode region If v DS < V GS - V TN MOSFET is in quadratic portion of the triode region

NJIT ECE271 Dr. Serhiy LevkovChap 4- 58 NMOS Transistor: Region SummaryIf v DS << V GS - V TN MOSFET is in linear portion of the triode region If v DS < V GS - V TN MOSFET is in quadratic portion of the triode region If v DS < V GS - V TN MOSFET is in saturation region and current saturates at (almost) constant value, independent of v DS . Discuss how to build the iv graph

NJIT ECE271 Dr. Serhiy LevkovChap 4- 59 Transconductance of a MOS Device Transconductance is the important characteristics that relates the change in drain current to a change in gate-source voltage

NJIT ECE271 Dr. Serhiy LevkovChap 4- 60 Transconductance of a MOS Device Transconductance is the important characteristics that relates the change in drain current to a change in gate-source voltage Taking the derivative of the expression for the drain current in saturation region,

NJIT ECE271 Dr. Serhiy LevkovChap 4- 61 Transconductance of a MOS Device Transconductance is the important characteristics that relates the change in drain current to a change in gate-source voltage Taking the derivative of the expression for the drain current in saturation region, The larger the device transconductance , the more gain we can expect from the amplifier that uses the transistor. Transconductance is inverse to the R on defined earlier and slightly differently.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 62 Channel-Length ModulationOn the previous iv -characteristics, the saturation part was horizontal (the current was constant, as v DS increases). However, it’s not exactly so.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 63 Channel-Length ModulationOn the previous iv -characteristics, the saturation part was horizontal (the current was constant, as v DS increases). However, it’s not exactly so. As v DS increases above v DSAT , length of depleted channel beyond pinch-off point, D L , increases and actual L decreases.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 64 Channel-Length ModulationOn the previous iv -characteristics, the saturation part was horizontal (the current was constant, as v DS increases). However, it’s not exactly so. As v DS increases above v DSAT , length of depleted channel beyond pinch-off point, D L, increases and actual L decreases. Since L is in denominator of the current expression, it compensate slightly the general increase of resistivity, which normally makes the curve flat.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 65 Channel-Length ModulationOn the previous iv -characteristics, the saturation part was horizontal (the current was constant, as v DS increases). However, it’s not exactly so. As v DS increases above v DSAT , length of depleted channel beyond pinch-off point, D L, increases and actual L decreases. Since L is in denominator of the current expression, it compensate slightly the general increase of resistivity, which normally makes the curve flat. As a result, i D increases slightly with v DS instead of being constant and we can rewrite equation in the form:

On the previous iv -characteristics, the saturation part was horizontal (the current was constant, as v DS increases). However, it’s not exactly so. As v DS increases above v DSAT , length of depleted channel beyond pinch-off point, D L, increases and actual L decreases. Since L is in denominator of the current expression, it compensate slightly the general increase of resistivity, which normally makes the curve flat. As a result, i D increases slightly with v DS instead of being constant and we can rewrite equation in the form: NJIT ECE271 Dr. Serhiy Levkov Chap 4- 66 Channel-Length Modulation where l is the channel length modulation parameter, depends on manufacturing and L. V a – Early voltage.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 67 Enhancement and Depletion Mode MOSFETSThe MOSFETS transistors can be of two types: enhancement mode when V TN > 0

NJIT ECE271 Dr. Serhiy LevkovChap 4- 68 Enhancement and Depletion Mode MOSFETSThe MOSFETS transistors can be of two types: enhancement mode when V TN > 0 depletion mode when V TN < 0 (the NMOS transistors considered so far were of enhancement type.)

NJIT ECE271 Dr. Serhiy Levkov Chap 4- 69Enhancement and Depletion Mode MOSFETS The MOSFETS transistors can be of two types: enhancement mode when V TN > 0 depletion mode when V TN < 0 (the NMOS transistors considered so far were of enhancement type.) The depletion mode devices are fabricated by ion implantation process used to form a built-in n -type channel in device to connect source and drain by a resistive channel.

NJIT ECE271 Dr. Serhiy Levkov Chap 4- 70Enhancement and Depletion Mode MOSFETS The MOSFETS transistors can be of two types: enhancement mode when V TN > 0 depletion mode when V TN < 0 (the NMOS transistors considered so far were of enhancement type.) The depletion mode devices are fabricated by ion implantation process used to form a built-in n -type channel in device to connect source and drain by a resistive channel. In such case, a non-zero drain current exists for v GS =0 , and a negative v GS required to turn device off.

NJIT ECE271 Dr. Serhiy Levkov Chap 4- 71Enhancement and Depletion Mode MOSFETS The MOSFETS transistors can be of two types: enhancement mode when V TN > 0 depletion mode when V TN < 0 (the NMOS transistors considered so far were of enhancement type.) The depletion mode devices are fabricated by ion implantation process used to form a built-in n -type channel in device to connect source and drain by a resistive channel. In such case, a non-zero drain current exists for v GS =0 , and a negative v GS required to turn device off. Depletion mode – because negative voltage has to be applied to the gate to deplete the n -type channel and eliminate the current path between the source and the drain.

NJIT ECE271 Dr. Serhiy Levkov Chap 4-72 Output and Transfer Characteristics of MOSFETS A MOSFET has one output variable – the drain-source current , that depends on two input variables – drain-source voltage and gate-source voltage ( V GS is usually is a control variable).

NJIT ECE271 Dr. Serhiy Levkov Chap 4-73 Output and Transfer Characteristics of MOSFETS A MOSFET has one output variable – the drain-source current , that depends on two input variables – drain-source voltage and gate-source voltage ( V GS is usually is a control variable). Two types of iv-curves are used to describe a MOSFET device fully: output (drain) curve (DS current vs. DS voltage for a fixed GS voltage) (the earlier considered characteristics were drain curves)

NJIT ECE271 Dr. Serhiy Levkov Chap 4-74 Output and Transfer Characteristics of MOSFETS A MOSFET has one output variable – the drain-source current , that depends on two input variables – drain-source voltage and gate-source voltage ( V GS is usually is a control variable). Two types of iv-curves are used to describe a MOSFET device fully: output (drain) curve (DS current vs. DS voltage for a fixed GS voltage) (the earlier considered characteristics were drain curves) transfer curve (DS current vs. GS voltage for a fixed DS voltage, f.i . sat .) Curves show that the enhancement mode device turns on at V GS = 2, while the depletion mode device turns on at V GS = -2. Example here

NJIT ECE271 Dr. Serhiy LevkovChap 4- 75 Body Effect or Substrate SensitivityNon-zero v SB changes threshold voltage. This is called substrate sensitivity and is modeled by where V TO - zero substrate bias for V TN (V) g - body-effect parameter ( )m, determines the intensity of the body effect 2F F - surface potential parameter (V), typically 0.6V. So far it was assumed that the source-bulk voltage v SB , is zero, which means that a MOSFET is a three terminal device. Quite often v SB , especially in ICs is no t zero. .

NJIT ECE271 Dr. Serhiy LevkovChap 4- 76 NMOS Summary (output characteristics)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 77 PMOS Transistors Structure (Enhancement-Mode) p -type source and drain regions in n -type substrate. n -type source and drain regions in p -type substrate. NMOS PMOS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 78 PMOS Transistors Structure (Enhancement-Mode) P -type source and drain regions in n -type substrate. v GS < 0 required to create p-type inversion layer in channel region N -type source and drain regions in p -type substrate. v GS > 0 required to create n -type inversion layer in channel region NMOS PMOS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 79 PMOS Transistors Structure (Enhancement-Mode) P -type source and drain regions in n -type substrate. v GS < 0 required to create p-type inversion layer in channel region For current flow, v GS < v TP N -type source and drain regions in p -type substrate. v GS > 0 required to create n -type inversion layer in channel region For current flow, v GS > v TN NMOS PMOS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 80 PMOS Transistors Structure (Enhancement-Mode) P -type source and drain regions in n -type substrate. v GS < 0 required to create p-type inversion layer in channel region For current flow, v GS < v TP To maintain reverse bias on diodes of source-substrate and drain-substrate junctions: v SB < 0 and v DB < 0 N -type source and drain regions in p -type substrate. v GS > 0 required to create n -type inversion layer in channel region For current flow, v GS > v TN To maintain reverse bias on the diodes of source-substrate and drain-substrate junctions: v SB >0 and v DB >0 NMOS PMOS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 81 Enhancement-Mode PMOS Transistors: Output Characteristics For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor .

NJIT ECE271 Dr. Serhiy LevkovChap 4- 82 Enhancement-Mode PMOS Transistors: Output Characteristics For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 83 Enhancement-Mode PMOS Transistors: Output Characteristics For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS Often, they are shown in the inverted scale and then they look very similar to the characteristics of NMOS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 84 Enhancement-Mode PMOS Transistors: Output CharacteristicsFor , transistor is off (note that on the diagram it’s v SG = - v GS ). For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS Often, they are shown in the inverted scale and then they look very similar to the characteristics of NMOS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 85 Enhancement-Mode PMOS Transistors: Output CharacteristicsFor , transistor is off (note that on the diagram it’s v SG = - v GS ). For more negative v GS , drain current increases in magnitude. For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS Often, they are shown in the inverted scale and then they look very similar to the characteristics of NMOS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 86 Enhancement-Mode PMOS Transistors: Output CharacteristicsFor , transistor is off (note that on the diagram it’s v SG = - v GS ). For more negative v GS , drain current increases in magnitude. PMOS is in triode region for small (absolute) values of V DS and in saturation for larger values (note that on the diagram it’s more negative to the right). For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS Often, they are shown in the inverted scale and then they look very similar to the characteristics of NMOS

NJIT ECE271 Dr. Serhiy LevkovChap 4- 87 NMOS Summary (model) For the enhancement-mode NMOS transistor, V TN > 0. For the depletion-mode NMOS, V TN < 0.

NJIT ECE271 Dr. Serhiy Levkov Chap 4-88 PMOS Summary (model) For the enhancement-mode PMOS transistor, V TP < 0. For the depletion-mode PMOS , V TP > 0.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 89 NMOS and PMOS Summary (regions of operation)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 90 NMOS and PMOS Summary (terminal voltages)

NJIT ECE271 Dr. Serhiy Levkov Chap 4-91 Short Summary of MOSFET (1)A MOSFET is a 3 terminal ( G ate, S ource, D rain) or 4 terminal ( G ate, S ource, D rain, B ody) electronic device -- it has input (usually v GS ) and output (usually i D ). The basic function of all transistors - an input voltage is used to provide the change in the output current (or voltage): the change in output can be much bigger then the change in the input - amplifier the change in output can be to turn it on or off – digital gate There are two types of MOSFET : PMOS and NMOS Both types exist in two modes: Enhancement and Depletion. NMOS enhancement mode: the output current (the inversion channel) may exist only when input ( v GS ) is positive (>0). NMOS depletion mode: the output current (the inversion channel) may exist when input ( v GS ) is zero, requires to apply v GS <0 to shut the current). PMOS is pretty much the complete inverse of NMOS.

NJIT ECE271 Dr. Serhiy Levkov Chap 4-92 Short Summary of MOSFET (2) NMOS Body: p -substrate Source, Drain: n + Inversion (conduction) layer: n E-NMOS Channel (drain current exists when v GS > 0) V TN > 0 D-NMOS Channel (drain current exists when v GS = 0) V TN <= 0 PMOS Body: n -substrate Source, Drain: p + Inversion (conduction) layer: p E-PMOS Channel (drain current exists when v GS < 0) V TP < 0 D-PMOS Channel (drain current exists when v GS = 0) V TP >= 0

NJIT ECE271 Dr. Serhiy Levkov Chap 4-93 Short Summary of MOSFET (3)MOSFET is a symmetrical device – D and S are interchangeable. MOSFET is fully described by two characteristics: - input-output or transfer characteristic: ( i D - v GS or v DS - v GS ) - output characteristic: ( i D – v DS ) All four types of MOSFET may operate in three regions: - cutoff : output current is 0 - triode: output current almost linearly depends on output voltage v DS (like in resistor) - saturation: output current almost does not depend on DS voltage v DS (like in diode) Transfer characteristics Output characteristics

NJIT ECE271 Dr. Serhiy LevkovChap 4- 94 MOSFET Circuit Symbols (g) and (i) are the most commonly used symbols in VLSI logic design. MOS devices are symmetric. In NMOS, n + region at higher voltage is the drain. In PMOS p + region at lower voltage is the drain

NJIT ECE271 Dr. Serhiy LevkovChap 4- 95 MOSFET AnalysisDepending on the type of application, a MOSFET may be put into one of three regions of operation by setting its operating Q-point .

NJIT ECE271 Dr. Serhiy LevkovChap 4- 96 MOSFET AnalysisDepending on the type of application, a MOSFET may be put into one of three regions of operation by setting its operating Q-point . For binary logic application the transistor acts like an “on-off” switch and the Q-point is set in ether cut-off region (“off”) or in the triode region (“on”) for the output characteristic or at the ends of transfer characteristic.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 97 MOSFET AnalysisDepending on the type of application, a MOSFET may be put into one of three regions of operation by setting its operating Q-point . For binary logic application the transistor acts like an “on-off” switch and the Q-point is set in ether cut-off region (“off”) or in the triode region (“on”) for the output characteristic or at the ends of transfer characteristic. For amplifier application, the Q-point is set in the saturation region for the output characteristic or in the middle (high) point of the transfer characteristic

NJIT ECE271 Dr. Serhiy LevkovChap 4- 98 MOSFET Analysis: logic inverter exampleFor the low values of input v GS (binary 0) the MOSFET is off, i D = 0 and v DS = v out = 5V  binary 1 . =low = 0 = 5

For v GS =5V (binary 1) the MOSFET is on , i D is high , and the output voltage v DS = v out = 0.65V  binary 0. NJIT ECE271 Dr. Serhiy Levkov Chap 4- 99 MOSFET Analysis: logic inverter example = 5 =high =0.6

NJIT ECE271 Dr. Serhiy LevkovChap 4- 100 MOSFET Analysis: logic inverter exampleFor the low values of input v GS (binary 0) the MOSFET is off, i D = 0 and v DS = v out = 5V  binary 1 . For v GS =5V (binary 1) the MOSFET is on , i D is high , and the output voltage v DS = v out = 0.65V  binary 0. = 5 =high =0.6 =low = 0 = 5

NJIT ECE271 Dr. Serhiy Levkov Chap 4- 101 MOSFET Analysis: amplifier example For the amplifier, the Q-point created by v GS = 2.5V is located at the high slope region of transfer characteristic and at the saturation region of the 2.5V curve. =2. 5

NJIT ECE271 Dr. Serhiy LevkovChap 4- 102 MOSFET Analysis: amplifier exampleFor the amplifier, the Q-point created by v GS = 2.5V is located at the high slope region of transfer characteristic and at the saturation region of the 2.5V curve. A small AC signal is added to vary the gate voltage about v GS = 2.5V, which causes the drain current to change significantly and amplified replica of the input appears at the drain. =2. 5

NJIT ECE271 Dr. Serhiy Levkov Chap 4-103 MOSFET Analysis: load line example From KVL for the right loop: v DD - v DS - i D R D = 0  i D = ( v DD - v DS )/ R D Setting two different values for v DS (5V and 3V for example) two points can be obtained and the load line drawn. Nonlinear element Thevenin equivalent

NJIT ECE271 Dr. Serhiy Levkov Chap 4-104 MOSFET Analysis: load line example From KVL for the right loop: v DD - v DS - i D R D = 0  i D = ( v DD - v DS )/ R D Setting two different values for v DS (5V and 3V for example) two points can be obtained and the load line drawn. Intersection with the transistor iv -curve gives the Q-point, which, of course, depends on the input v GS . Conclusion The same device in the similar circuits may behave differently depending on the ‘biasing‘ – DC voltages applied to different terminals of MOSFET. The ‘signal’ then, is actually comprised of relatively small changes in the DC current and/or voltage bias. Nonlinear element Thevenin equivalent

NJIT ECE271 Dr. Serhiy LevkovChap 4- 105 Bias Analysis ApproachThe previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used:

NJIT ECE271 Dr. Serhiy LevkovChap 4- 106 Bias Analysis ApproachThe previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used: Assume an operation region (generally the saturation region)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 107 Bias Analysis ApproachThe previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used: Assume an operation region (generally the saturation region) Use circuit analysis to find V GS (left, input loop)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 108 Bias Analysis ApproachThe previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used: Assume an operation region (generally the saturation region) Use circuit analysis to find V GS (left, input loop) Use V GS to calculate I D , and I D to find V DS (right, output loop)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 109 Bias Analysis ApproachThe previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used: Assume an operation region (generally the saturation region) Use circuit analysis to find V GS (left, input loop) Use V GS to calculate I D , and I D to find V DS (right, output loop) Check validity of operation region assumptions Change assumptions and analyze again if required. NOTE : An enhancement-mode device with V DS = V GS is always in saturation. Why? For pinch off: V DS >= V GS - V TN . If V DS = V GS , then V DS >= V DS - V TN , or V TN >= 0, which is always true for E-MOS device.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 110 Problem: Find Q-pt (ID, VDS , V GS ) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region . Bias Analysis 1- Constant GS Voltage Biasing (1) Do this example on the board

NJIT ECE271 Dr. Serhiy LevkovChap 4- 111 Problem: Find Q-pt (ID, VDS , V GS ) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region. Assumption: 1. Transistor is saturated. 2. I G =I B =0. Bias Analysis 1- Constant GS Voltage Biasing (1)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 112 Analysis: Simplify circuit with Thevenin transformation to find VEQ and R EQ for gate-bias voltage. Bias Analysis: Ex.1- Constant GS Voltage Biasing (1) Problem: Find Q-pt ( I D , V DS , V GS ) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region. Assumption: 1. Transistor is saturated. 2. I G =I B =0.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 113 Analysis: Simplify circuit with Thevenin transformation to find VEQ and R EQ for gate-bias voltage. Find V GS from the input loop, and then use this to find I D . Problem: Find Q-pt ( I D , V DS , V GS ) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region. Assumption: 1. Transistor is saturated. 2. I G =I B =0. Bias Analysis 1- Constant GS Voltage Biasing (1)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 114 Analysis: Simplify circuit with Thevenin transformation to find VEQ and R EQ for gate-bias voltage. Find V GS from the input loop, and then use this to find I D . With I D , we can then calculate V DS using the output loop Problem: Find Q-pt ( I D , V DS , V GS ) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region. Assumption: 1. Transistor is saturated. 2. I G =I B =0. Bias Analysis 1- Constant GS Voltage Biasing (1)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 115 The left (input) loop . Since I G =0: Then, from the transistor equation: Bias Analysis 1- Constant GS Voltage Biasing (1)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 116 The left (input) loop . Since I G =0: Check: V DS >V GS -V TN . Hence saturation region assumption is correct. Q-pt: (50.0 m A, 5.0 V) with V GS = 3.0V Discussion. The obtained result is proportional to K and to the square of V TN , thus Q-pt. is quite sensitive to the parameter fluctuation of the device, so this circuit is not very used. The right (output) loop : Then, from the transistor equation: Bias Analysis 1- Constant GS Voltage Biasing (1)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 117 Check:VDS>VGS-VTN . Hence saturation region assumption is correct. Q-pt: (54.5 m A , 4.55 V) with V GS = 3.00 V Now let’s repeat the same problem taking into account channel length modulation . Bias Analysis 1- Constant GS Voltage Biasing (2)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 118 Check:VDS>VGS-VTN . Hence saturation region assumption is correct. Q-pt: (54.5 m A , 4.55 V) with V GS = 3.00 V Discussion. The bias levels have changed by about 10%. Typically, component values will vary more than this, so there is little value in including  effects in most circuits. Now let’s repeat the same problem taking into account channel length modulation . Bias Analysis 1- Constant GS Voltage Biasing (2)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 119 Problem: Find Q-pt (ID, VDS , V GS ) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumptions: 1. I G =I B =0. Do we need assumption for the transistor region of operation? Load Line Analysis. Bias Analysis 1- Constant GS Voltage Biasing (3)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 120 Problem: Find Q-pt (ID, VDS , V GS ) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumptions: 1. I G =I B =0. 2. No need for region assumption, will find solution directly. Load Line Analysis. Bias Analysis 1- Constant GS Voltage Biasing (3)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 121 Analysis: First, simplify circuit with Thevenin transformation to find VEQ and R EQ for gate-bias voltage Load Line Analysis. Problem: Find Q-pt ( I D , V DS , V GS ) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumptions: 1. I G =I B =0. 2. No need for region assumption, will find solution directly. Bias Analysis 1- Constant GS Voltage Biasing (3)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 122 Analysis: First, simplify circuit with Thevenin transformation to find VEQ and R EQ for gate-bias voltage Load Line Analysis. The left (input) loop . Since I G =0: Problem: Find Q-pt ( I D , V DS , V GS ) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumptions: 1. I G =I B =0. 2. No need for region assumption, will find solution directly. Bias Analysis 1- Constant GS Voltage Biasing (3)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 123 Check: The load line approach agrees with previous calculation. Q-pt: (50.0 mA, 5.00 V) with V GS = 3.00 V Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region. @ V DS =0, I D =100uA, @ I D =0, V DS =10V Plotting on device characteristic yields Q-pt at intersection with V GS = 3V device curve. Load Line Analysis . From the KVL for the right loop , load line becomes Bias Analysis 1- Constant GS Voltage Biasing (3)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 124 Bias Analysis 2 - Four-Resistor Biasing (1) Problem: Find Q-pt ( I D , V DS ) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Assumption: Transistor is saturated, I G =I B =0 Analysis: First, simplify circuit, split V DD into two equal-valued sources and apply Thevenin transformation to find V EQ and R EQ for gate-bias voltage Do this example on the board

NJIT ECE271 Dr. Serhiy LevkovChap 4- 125 Left loop. Since I G =0, Bias Analysis 2 - Four-Resistor Biasing (1)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 126 Left loop. Since I G =0, If V GS = -2.71 , V GS <V TN and MOSFET will be cut-off. Thus and I D = 34.4 m A Solution: Bias Analysis 2 - Four-Resistor Biasing (1)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 127 Left loop. Since I G =0, If V GS = -2.71 , V GS <V TN and MOSFET will be cut-off. Thus and I D = 34.4 m A We have V DS >V GS -V TN . Hence saturation region assumption is correct. Q-pt: (34.4 m A , 6.08 V) with V GS = 2.66 V Solution: Right loop . Bias Analysis 2 - Four-Resistor Biasing (1)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 128 Estimate value of ID and use it to find V GS and V SB Use V SB to calculate V TN Find I D ’ using last equation If I D ’ is not same as original I D estimate, start again. In previous example, the body terminal was connected to the source, so V SB = 0. Now let’s consider the case with Iterative solution can be found by following steps: Bias Analysis 2 - Four-Resistor Biasing (2) Body Effect

NJIT ECE271 Dr. Serhiy LevkovChap 4- 129 The iteration sequence leads to ID= 88.0 mA, VTN = 1.41 V, We obtained that V DS >V GS -V TN . Hence saturation region assumption is correct. Q-pt: (88.0 m A , 6.48 V) Check: V DS > V GS - V TN , therefore still in active region. Discussion: Body effect has decreased current by 12% and increased threshold voltage by 40%. Bias Analysis 2 - Four-Resistor Biasing (2) Body Effect

NJIT ECE271 Dr. Serhiy LevkovChap 4- 130 Do this example on the board Assumption: 1. I G =I B =0. 2. Transistor is saturated since V DS =V GS Bias Analysis 3 – Two Resistor (saturation)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 131 Bias Analysis 3 – Two Resistor (saturation) Assumption: 1. I G =I B =0. 2. Transistor is saturated since V DS =V GS Analysis. No need for input loop: V DS =V GS Output loop:

NJIT ECE271 Dr. Serhiy LevkovChap 4- 132 If V GS = -0.769 , V GS <V TN and MOSFET will be cut-off. Thus and I D = 130 m A We obtained V DS >V GS -V TN . Hence saturation region assumption is correct. Q-pt: (130 m A, 2.00 V) Assumption: 1. I G =I B =0. 2. Transistor is saturated since V DS =V GS Analysis. No need for input loop: V DS =V GS Output loop: Bias Analysis 3 – Two Resistor (saturation)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 133 Discussion of Four and Two-Resistor BiasingFour resistorProvide excellent bias for transistors in discrete circuits. Stabilize bias point with respect to device parameter and temperature variations using negative feedback. Use single voltage source to supply both gate-bias voltage and drain current. Generally used to bias transistors in saturation region in amplifier circuits. Two-resistor Uses lesser components that four-resistor biasing and also isolates drain and gate terminals. Feedback mechanism. Suppose, for some reason I D begins to increase. From it follows that V GS has to decrease, since V g is constant. This will decrease the current I D due to current equation, thus restoring the existing state.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 134 Assumption: 1. I G =I B =0 2. Transistor is saturated. Analysis. Left loop: V GS =V DD = 4 V Bias Analysis 4 – One Resistor (triode) Do this example on the board

NJIT ECE271 Dr. Serhiy LevkovChap 4- 135 Assumption: 1. I G =I B =0 2. Transistor is saturated. Analysis. Left loop: V GS =V DD = 4 V Right loop: Bias Analysis 4 – One Resistor (triode)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 136 Assumption: 1. I G =I B =0 2. Transistor is saturated. Analysis. Left loop: V GS =V DD = 4 V and I D =1.06 mA We obtained V DS <V GS -V TN , transistor is in triode region Q-pt :(1.06 mA, 2.3 V) Bias Analysis 4 – One Resistor (triode) Right loop: We obtained V DS <V GS -V TN . Hence, saturation region assumption is incorrect. Assume the triode region and use the triode region equation:

NJIT ECE271 Dr. Serhiy LevkovChap 4- 137 Bias Analysis 5 - Two-Resistor, PMOST Assumption: 1. I G =I B =0 2. Transistor is saturated: V DS =V GS Analysis . Left loop: no need, V DS =V GS Right loop: Since V GS = -0.369 V is more than V TP = -2 V, we take V GS = -3.45 V Then we can calculate I D = 52.5 m A . Check: Hence saturation assumption is correct. Q-pt: (52.5 m A, -3.45 V) Do this example on the board

NJIT ECE271 Dr. Serhiy LevkovJunction Field-Effect Transistors (JFET) Chap 4- 138

NJIT ECE271 Dr. Serhiy LevkovJunction Field-Effect Transistors (JFET) n- channel JFET consists of: n -type semiconductor block that houses the channel region in n -channel JFET. pn junction - forms the gate. Source and drain terminals Chap 4- 139 MOSFET devices are called FET because electric field is used to control the shape and hence the conductivity of the channel of one type charge carrier ( p or n ) in semiconductor device. There is another type of FET, which is not using MOS capacitor structure, however utilizes the electric filed effect: Junction Field-Effect Transistor. Less prevalent than MOSFET, JFET have many uses, especially in analog RF applications. Can be of two types: n -channel and p -channel JFET. Like a diode with enlarged n -type section and two n -terminals.

NJIT ECE271 Dr. Serhiy LevkovJFET Structure In triode region, JFET is a voltage-controlled resistor, r - resistivity of channelL - channel length W - channel width between pn junction depletion regions t - channel depth With no bias applied, a resistive channel exists. The current enters channel at the drain and exits at source. The resistance of the drain-source channel is controlled by changing the physical width of the channel through modulation of the depletion layers around pn -junctions (like squeezing a garden hose) Application of reverse bias to the gate-channel diodes causes the depletion layer to widen, reducing the channel width and decreasing the current. JFET is inherently a depletion-mode device – a voltage must be applied to turn the device off. Chap 4- 140

NJIT ECE271 Dr. Serhiy LevkovJFET: applying Gate-Source voltage Chap 4- 141 v GS = 0. The channel width is W. It can conduct current well if v DS is applied.

NJIT ECE271 Dr. Serhiy LevkovJFET: applying Gate-Source voltage Chap 4- 142 v GS = 0. The channel width is W. It can conduct current well if v DS is applied. V P < v GS <0. The depletion layers width is increased. The channel width W’ < W, and channel resistance increases. Gate-source junction is reverse-biased, i G almost 0.

NJIT ECE271 Dr. Serhiy LevkovJFET: applying Gate-Source voltage vGS = 0. The channel width is W. It can conduct current well if vDS is applied . V P < v GS < 0. The depletion layers width is increased. The channel width W ’ < W, and channel resistance increases. Gate-source junction is reverse-biased, i G almost 0. v GS = V P < 0. The depletion layer is max. Channel width – zero, region is pinched-off , channel resistance is infinite . Chap 4- 143

NJIT ECE271 Dr. Serhiy LevkovJFET: applying Drain-Source voltage With constant v GS, depletion region near drain increases with vDS Chap 4- 144

NJIT ECE271 Dr. Serhiy LevkovJFET: applying Drain-Source voltage With constant v GS, depletion region near drain increases with vDS At v DSP = v GS - V P , channel is totally pinched-off; i D is saturated . ( the current does not stop: electrons are accelerated down the channel (V is large), are injected into the depletion region and swept to the drain) Chap 4- 145

NJIT ECE271 Dr. Serhiy LevkovJFET: applying Drain-Source voltage With constant v GS, depletion region near drain increases with vDS At v DSP = v GS - V P , channel is totally pinched-off; i D is saturated . ( the current does not stop: electrons are accelerated down the channel (V is large), are injected into the depletion region and swept to the drain) JFET also suffers from channel-length modulation like MOSFET at larger values of v DS . Chap 4- 146

NJIT ECE271 Dr. Serhiy LevkovJFET: applying Drain-Source voltage With constant v GS, depletion region near drain increases with vDS At v DSP = v GS - V P , channel is totally pinched-off; i D is saturated . ( the current does not stop: electrons are accelerated down the channel (V is large), are injected into the depletion region and swept to the drain) JFET also suffers from channel-length modulation like MOSFET at larger values of v DS . Chap 4- 147 http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/jfet.html http://learnabout-electronics.org/fet_03.php Simulation:

NJIT ECE271 Dr. Serhiy LevkovN -Channel JFET i-v Characteristics Transfer Characteristics Output Characteristics Chap 4- 148 The JFET iv- characteristics are remarkably similar to the MOSFET characteristics (virtually identical).

NJIT ECE271 Dr. Serhiy LevkovN -Channel JFET i-v equations Equations are similar to MOSFET except written slightly differently For all regions :In cutoff region: In Triode region: In pinch-off region: Explanation: Chap 4- 149 Typically:

NJIT ECE271 Dr. Serhiy LevkovP -Channel JFETPolarities of n- and p-type regions of the n-channel JFET are reversed to get the p -channel JFET. Channel current direction and operating bias voltages are also reversed. Chap 4- 150

NJIT ECE271 Dr. Serhiy LevkovJFET Circuit Symbols JFET structures are symmetric like MOSFETs.Source and drain determined by circuit voltages. Chap 4- 151 n -channel p -channel

NJIT ECE271 Dr. Serhiy LevkovJFET n-Channel Model Summary Chap 4-152

NJIT ECE271 Dr. Serhiy LevkovJFET p-Channel Model Summary Chap 4-153

NJIT ECE271 Dr. Serhiy Levkov Biasing JFET (1) Assumptions: Gate-channel junction is reverse-biased, reverse leakage current of gate, I G = 0 N -channel JFET Depletion-mode MOSFET Chap 4- 154

NJIT ECE271 Dr. Serhiy Levkov Biasing JFET (2) DIY Chap 4-155

NJIT ECE271 Dr. Serhiy LevkovRegion Assumption : JFET is pinched-off (saturation) Since V GS = -13.1 V is less than V P = -5 V , we take V GS = -1.91 V (n-channel type!) and, I D = I S = 1.91 mA . Output loop: V DS >V GS -V P . Hence pinch-off region assumption is correct and gate-source junction is reverse-biased by 1.91V. Q-pt: (1.91 mA , 6.27 V) Chap 4- 156 Biasing JFET (3)

NJIT ECE271 Dr. Serhiy LevkovChap 4- 157 Internal Capacitances in Electronic DevicesLimit high-frequency performance of the electronic device they are associated with. Limit switching speed of circuits in logic applications Limit frequency at which useful amplification can be obtained in amplifiers. MOSFET capacitances depend on operation region and are non-linear functions of voltages at device terminals.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 158 NMOS Transistor Capacitances: Triode RegionCox ” =Gate-channel capacitance per unit area(F/m 2 ). C GC =Total gate channel capacitance. C GS = Gate-source capacitance. C GD =Gate-drain capacitance. C GSO and C GDO = overlap capacitances (F/m). C SB = Source-bulk capacitance. C DB = Drain-bulk capacitance. A S and A D = Junction bottom area capacitance of the source and drain regions. P S and P D = Perimeter of the source and drain junction regions.

NJIT ECE271 Dr. Serhiy LevkovChap 4- 159 NMOS Transistor Capacitances: Saturation RegionDrain no longer connected to channel

NJIT ECE271 Dr. Serhiy LevkovChap 4- 160 NMOS Transistor Capacitances: Cutoff RegionConducting channel region completely gone. C GB = Gate-bulk capacitance C GBO = gate-bulk capacitance per unit width.

NJIT ECE271 Dr. Serhiy LevkovJFET Capacitances CGD and CGS are determined by depletion-layer capacitances of reverse-biased pn junctions forming gate and are bias dependent. Chap 4- 161

NJIT ECE271 Dr. Serhiy LevkovChap 4- 162SPICE Model for NMOS Transistor Typical default values used by SPICE: K n or K p = 20 m A/V 2 g = 0 l = 0 V TO = 1 V m n or m p = 600 cm 2 /V.s 2 F F = 0.6 V C GDO = C GSO =C GBO =C JSW = 0 T ox = 100 nm

NJIT ECE271 Dr. Serhiy LevkovSPICE Model for JFET Typical default values used by SPICE: Vp = -2 V l = C GD = C GD = 0 Transconductance parameter BETA BETA = I DSS /V P 2 = 100 m A/V 2 Chap 4- 163