PPT-1 Lecture: Branch Prediction, Out-of-order Processors

Topics branch predictors outoforder intro register renaming 2 2Bit Bimodal Prediction For each branch maintain a 2bit saturating counter if the branch is taken counter min3counter1. Static Branch Prediction. Code around delayed branch. To reorder code around branches, need to predict branch statically when compile . Simplest scheme is to predict a branch as taken. Average misprediction = untaken branch frequency = 34% SPEC. (. iPhone. 3G). Jeff Brantley. Chris Gregg. Bill . Stitson. Processor Overview. Features. Designed for consumer and wireless products . RISC Processor with Harvard Architecture. Vector Floating Point coprocessor. CS 3220. Fall 2014. Hadi Esmaeilzadeh. hadi@cc.gatech.edu. . Georgia Institute of Technology. Some slides adopted from Prof. . Milos . Prvulovic. Control Hazards Revisited. Forwarding helps a lot with data hazards. Debajit. B. h. attacharya. Ali . JavadiAbhari. ELE 475 Final Project. 9. th. May, 2012. Motivation. Branch Prediction. Simulation Setup & Testing Methodology. Dynamic Branch Prediction. Single Bit Saturating Counter. 5. Branch Prediction . (2.3) and . Scoreboarding. (A.7). 2. Why do we want to predict branches?. MIPS based pipeline – 1 instruction issued per cycle, branch hazard of 1 cycle.. Delayed branch. Modern processor and next generation – multiple instructions issued per cycle, more branch hazard cycles will incur.. Smruti. R. Sarangi. Contents. In-order Pipelines. Out-of-order Pipelines: Motivation. Out-of-order Pipelines: Basics. Branch Prediction. Pipelines. What do we know up till now: . In-order Pipelines. Computer Architecture and Implementation. Montek Singh. Oct 10, 2016. Topic: . Instruction-Level . Parallelism - . I. (Dynamic Branch Prediction). Instruction-Level Parallelism. Exploit . parallelism . Branch Prediction. Static Branch Prediction. To reorder code around branches, we need to predict branch statically when compiling. Always taken / not taken. Can be compiler directed. Delayed Branch . As we saw last week, dynamic instruction issue allows us to exploit as much parallelism as exists in instruction code. Our stalling situations are limited to finite resources, cache misses and branches. Smruti. R. Sarangi. Contents. In-order Pipelines. Out-of-order Pipelines: Motivation. Out-of-order Pipelines: Basics. Branch Prediction. Pipelines. What do we know up till now: . In-order Pipelines. As we saw last week, dynamic instruction issue allows us to exploit as much parallelism as exists in instruction code. Our stalling situations are limited to finite resources, cache misses and branches. Contents. In-order Pipelines. Out-of-order Pipelines: Motivation. Out-of-order Pipelines: Basics. Branch Prediction. Pipelines. What do we know up till now: . In-order Pipelines. Instructions enter the pipeline in program order. Address prediction and recovery. (And interrupt recovery too.). Announcements:. Programming assignment #2 . Due today. Extending to midnight.. HW . #2 due . Monday 2/3. P3 posted . tonight. Reading. Draw a state machine for a 2 bit branch prediction scheme . Explain the impact on the compiler of branch delay. . Chapter 4 — The Processor — . 2. Control Hazards. Consider:. . add $t1, $zero, $zero # .