GBT-FPGA Tutorial Introduction - PowerPoint Presentation

Slide1

GBT-FPGA Tutorial

Introduction

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

1

Slide2

Schedule11:00 – 12:30: Introduction to the GBT-FPGA

General overviewGBT-FPGA structureHow to importing the GBT-FPGA into your project ?

13:25 – 15:00: How to use the GBT-FPGA IP in standard modeDemo setup (Arria

10 based)How to create a reference design from scratch ?How to debug the design ?

15:20 – 16:20: How to use the GBT-FPGA IP in latency-optimized mode

How to improve the design to use the latency-optimized mode ?

How to debug the design ?16:20 – 17:00: How to use an existing reference design (KC705)17:00 – 18:00: Tips and tricks

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

2

Slide3

GBT-FPGA Tutorial

Overview: code structure

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

3

Slide4

OutlineGeneral overview

SVN Repository architectureImport the GBT-FPGA IP into my project

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

4

Slide5

General overviewWhat is the GBT-FPGA ?

Project initiated in 2009Library to emulate a GBT serdes in an FPGA (e-links not handled)

Targets FPGA from Altera and XilinxSupported by EP-ESE-BE section at CERN

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

5

Slide6

GBTx

FE

Module

FE

Module

Phase – Aligners + Ser/Des for E – Ports

FE

Module

E – Port

E – Port

E – Port

GBT – SCA

E – Port

Phase - Shifter

E – Port

E – Port

E – Port

E – Port

CDR

DEC/DSCR

SER

SCR/ENC

I2C Master

I2C Slave

Control Logic

Configuration

(e-Fuses +

reg

-Bank)

Clock[7:0]

CLK Manager

CLK Reference/

xPLL

External clock reference

clocks

control

data

One 80 Mb/s port

I2C

Port

I2C (light)

JTAG

JTAG

Port

80, 160 and 320 Mb/s ports

GBTIA

GBLD

GBTX

e-Link

clock

data-up

data-down

ePLLTx

ePLLRx

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

6

Slide7

GBTx serial streams

Downstream: GBT framesScramblerReed Solomon encoder

Interleaver

HEADER

3..0

IC

1..0

DATA

79..0

EC

1..0

FEC

31..0

Upstream:

GBT frames…

… or

Widebus

frames

HEADER

3..0

IC

1..0

DATA

79..0

EC

1..0

FEC

31..0

HEADER

3..0

IC

1..0

DATA

111..0

EC

1..0

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

7

Slide8

GBT Frame

4

60

H<3:0>

SC<3:0>

D<79:0>

FRM<119:0>

80

21

21

21

21

21

21

21

21

4

Scrambler

Scrambler

Scrambler

Scrambler

44

44

60

120

RS Encoder

RS Encoder

Interleaving

“randomization” of the data

to ensure a good balance of the signal

Ad-hoc encoding scheme allowing the

correction of 2 symbols of 4 bits per encoder

Adding the interleaving

a

llows having up to 16

c

onsecutive bit errors to

b

e decoded

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

8

Slide9

GBT Frame

The frame is shifted out MSB first, that is: FRM<119>, FRM<118>, … FRM<0> (The header shifts out first)

Interleaving

RS Encoding

Scrambling

H<3:0>

SC<3:0>

D<20:0>

D<79:63>

SCR<20:0>

SCR<83:63>

SCR<41:0>

FEC<15:0>

SCR<43:42>

SCR<83:44>

FEC<31:16>

H<3:0>

D<41:21>

D<62:42>

SCR<41:21>

SCR<62:42>

FRM<119:0>

FRM<119>

FRM<0>

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

9

Slide10

GBT Frame construction vs elink modes

HEADER

3..0

IC

1..0

Elink39

Bits 1..0

EC

1..0

FEC

31..0

Elink38

Bits 1..0

Elink37

Bits 1..0

Elink32

Bits 1..0

Group 4

Group 0

HEADER

3..0

IC

1..0

Elink38

Bits

3

..0

EC

1..0

FEC

31..0

Elink36

Bits 3..0

Elink34

Bits 3..0

Elink32

Bits 3..0

Elink3

Bits

3

..0

Elink2

Bits 3..0

Elink1Bits 3..0

Elink0Bits 3..0

Group 4

Group 0

x2x4x8

HEADER3..0

IC1..0EC1..0

FEC31..0

Elink36Bits 7..0

Elink32Bits 7..0

Group 4

Group 0Elink36

Bits 1..0Elink35Bits 1..0Elink34Bits 1..0

Elink33

Bits 1..0

Elink4

Bits 7..0

Elink0Bits 7..0

Elink7Bits 1..0

Elink6Bits 1..0

Elink5

Bits 1..0

Elink0

Bits 1..0

Elink4

Bits 1..0

Elink3

Bits 1..0

Elink2Bits 1..0

Elink1

Bits 1..0

27/06/2016

GBT-FPGA Tutorial – 27/06/201610

Slide11

Downstream Elink mode «x2» (80Mb/s)

HEADER

3..0

IC

1..0

DATA

79..0

EC

1..0

FEC

31..0

GBTx

40 «

elinks

»

packets

of 2 bits on

each

80bits frame @ 40MHz + 1 Slow Control

link

40 + 1 serial links @ 80Mbps

Dio

[0]

Dout

[38]

Dout

[39]

SC

eport

GBTx

Serdes

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

11

Slide12

Downstream Elink mode «x4» (160Mb/s)

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

12

HEADER

3..0

IC

1..0

DATA

79..0

EC

1..0

FEC

31..0

GBTx

20 «

elinks

»

packets

of

4

bits on

each

120bits frame @ 40MHz + 1 slow control

link

20 serial links @ 160Mbps

Dio

[0]

Dio

[1]

…

Dout

[37]

Dout

[38]

Dout

[39]

SC

eport

GBTx

Serdes

Slide13

Downstream Elink mode «x4» (320Mb/s)

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

13

HEADER

3..0

IC

1..0

DATA

79..0

EC

1..0

FEC

31..0

GBTx

1

0 «

elinks

»

packets

of 8 bits on

each

120bits frame @ 40MHz + 1 slow control

link

1

0 serial links @ 320Mbps

Dio

[0]

….

Dout

[35]

Dout

[36]

Dout

[37]

Dout

[38]

Dout

[39]

SC

eport

GBTx

Serdes

Slide14

General overview27/06/2016

GBT-FPGA Tutorial – 27/06/2016

14

Slide15

General overviewWhat is the GBT-FPGA ?

TX_FRAMECLK

40MHz

240MHz or 120MHz

Tx

PLL

240MHz or 120MHz

REFCLK

TX_USRCLK

Encoder

GBT-Frame

Wide-Bus

TX_ISDATA_SEL

Scrambler

WB_EXTRADATA

32bit

84bit

GBT_DATA

120bit

120bit

120bit

Gearbox

(Register)

20 or 40 bit

PISO

Serial clock

Transmitter

TX

Link n

GBT BANK

R

X_FRAMECLK

40MHz

RX_USRCLK

Encoder

GBT-Frame

Wide-Bus

RX_ISDATA_FLAG

Descrambler

WB_EXTRADATA

32bit

84bit

GBT_DATA

120bit

Gearbox

(Register)

RX

Link n

120bit

Barrel shifter

Pattern search

BitSlip

control

RX

Frameclk

gen.

240MHz or 120MHz

20 or 40 bit

CDR

SIPO

Barrel Shifter

RXRECCLK Phase

Algnr

/

Receiver

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

15

Slide16

General overviewWhat encoding are supported ?

GBT: based on Reed-SalomonUser data: 84bitCan correct up to 4 consecutive symbols (4bit)

WideBus:

User data: 112bitNo Forward Error Correction (FEC)What are the mode supported ?

Standard mode

Latency: Non fixed, non deterministic and “high”

Easier to implementLatency-optimized mode:Latency: Fixed, deterministic

and lowComplex to implement

GBT Frame

WideBus

Frame

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

16

Slide17

General overviewWhat are the FPGAs characteristics?

FPGA

Mode

Encoding

Manufacturer

Device

Standard

Lat

-optimized

GBT

WideBus

Altera

Cyclone V

Yes

No

Tx

/Rx

Tx

/Rx

Stratix

V

Yes

Yes

Tx

/Rx

Tx

/Rx

Arria

V

Yes

Yes

Tx

/Rx

Tx

/Rx

Arria

10

Yes

Yes

Tx

/Rx

Tx

/Rx

Xilinx

Virtex

6

Yes

Yes

Tx

/Rx

Tx

/Rx

Virtex

7

Yes

Yes

Tx

/Rx

Tx

/Rx

Kintex

7

Yes

Yes

Tx

/Rx

Tx

/Rx

Kintex

Ultrascale

Yes

Yes

Tx

/Rx

Tx

/Rx

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

17

Slide18

SVN Repository architectureHow to get the latest version of the GBT-FPGA IP ?

SVN: https://svn.cern.ch/reps/ph-ese/be/gbt_fpga/tags/<tag>Latest tag: GBT_FPGA_4_0_0

Foreseen: GBT_FPGA_4_0_1 (July 2016)Major bug fix:

gbt_rx_decoder_gbtframe_chnsrch and gbt_rx_framealigner_pattsearch instances

Are there any additional implementation ?

YES, different branches

SVN: https://svn.cern.ch/reps/ph-ese/be/gbt_fpga/branch/<branch>E.g: GBT_FPGA_4_0_0_KC705_240MHZ

Recommended tool: Tortoise SVN

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

18

Slide19

DEMO

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

19

Slide20

SVN Repository architecture

altera_a10

altera_cv

altera_sv

xilinx_k7v7

xilinx_v6

core_sources

altera_a10

altera_cv

altera_sv

xilinx_k7v7

xilinx_v6

core_sources

example design

gbt_bank

tcl

GBT_FPGA_4_0_0 Tag

Example designs:

Arria

10 : PCIe40 and Altera GX development kit

Cyclone V : Altera GT development kit

Stratix

V : AMC40 (with multi-links with

Tx

Lat

-opt)

Kintex7 : FC7 and KC705

Virtex7 : VC707

Virtex

6 : ML605 and Glib

IP Core:

core_sources

: encoding/decoding modules

altera

_* and

xilinx

_*: Device specific (e.g.: transceivers)

TCL:

TCL script to source files

QSYS component description (Altera)

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

20

Slide21

SVN Repository architectureWhat is the architecture of a reference design?

Board specific entity

Device specific entity

GBT Bank

Data pattern gen.

Data pattern check.

RX

FrameClk

generator

Signal tap

In-system sources & probes

Additional modules:

-

Freq

monitoring

- PLL controller

- JTAG server & GPIO

- …

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

21

Slide22

DEMO

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

22

Slide23

SVN Repository architectureWhat modules are the modules included in the GBT-FPGA repository?

GBT-FPGA IP: Main module of the GBT-FPGA. It contains the encoder/decoder, transceivers …Clocking modules:RX

Frameclk alignerClock divider

Clock frequency measurementData modules:GBT Data pattern generatorGBT Data pattern checker

Latency measurement:

Data pattern

matchflagLatency measurementThese modules will be used and detailed during the creation of the reference design

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

23

Slide24

DEMO

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

24

Slide25

Import the GBT-FPGA IP into my project

How to use the TCL scripts?Modification of the TCL file using an editor

Import it in the project: “source

mytclfile.tcl”

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

25

Slide26

DEMO

27/06/2016

GBT-FPGA Tutorial – 27/06/2016

26