PPT-0 Trusted Design In FPGAs

Steve Trimberger Xilinx Research Labs 1 Security Challenges How to securely authenticate devices Keycards RFIDs mobile phones Genuine electronics vs counterfeits How to protect sensitive IP on devices. Attestation. Dane Brandon, . Hardeep. . Uppal. CSE551. University of Washington. Overview. Motivation. Trusted Computing and Trusted Platform Modules (TPM). Trusted Software Stacks. Attestation. Measurements. . ARCHITECTURE. 1. Agenda. Introduction. Partial Reconfiguration Basics. Design Considerations. Advantages of Partial Reconfiguration. Challenges of Partial Reconfiguration. Application Examples. Part 1. Objectives. After completing this module, you will be able to:. Describe the dedicated hardware IP that is included with the 7 series FPGAs. Serial Gigabit Transceivers. PCI Express Technology Interface. Eric LaForest, Ming Liu, Emma Rapati, and Greg Steffan. ECE, University of Toronto. Multi-Ported Memories (MPM). MPM: Memory with more than 2 ports. Many uses:. register files. queues/buffers. FPGA BRAMs:. Implementing Portable Biomedical Applications. Shahin. . Lotfabadi. Agenda . Objectives. Auto-Regressive (AR) Modeling. Overview Of The FPGA Implementation of AR Burg Algorithm. Subthreshold Circuit Design. Fundamentals of . FPGA Design. 1. day. Designing for. Performance. 2. days. Advanced FPGA. Implementation. 2. days. Intro to VHDL or . Intro to Verilog. 3. days. FPGA and ASIC Technology Comparison. FPGA vs. ASIC Design Flow. of A . 45nm SLC 3D NAND Flash . CPLD. Arijit Banerjee and Sergiu Mosanu. Date: 5/15/2015. Device scaling has reached molecular dimensions. 2D Moore’s law is about to end. 3D can be an option to further device scaling. BY. LI HONGJUAN, LANYUQING. The presenter. Rusul. J. . ALSaedi. Spring 2015. CS 69995- Dr. Rothstein. Contents. Abstract. Introduction. Design process of trusted operating system based on Linux. A. Eric LaForest, Ming Liu, Emma Rapati, and Greg Steffan. ECE, University of Toronto. Multi-Ported Memories (MPM). MPM: Memory with more than 2 ports. Many uses:. register files. queues/buffers. FPGA BRAMs:. Seyi. Ayorinde. University of Virginia. February 12. th. , 2015. Context. BIST for FPGAs is now a mature study. Many examples of different BIST methodologies and implementations. BIST for FPGAs has been realized on commercial FPGAs primarily. Stream Cyphers. . Shemal Shroff. Shoaib. . Bhuria. Yash. . Naik. Peter Hall. outline. Introduction to Security. Relevance to FPGA. Design and Manufacture flow for an FPGA. Things to secure and why?. Jason Gilmore (Texas A&M University). Ben . Bylsma. (The Ohio State University). Workshop on FPGAs in HEP, 21 March 2014. Considerations . for SEUs in FPGAs. Configuration memory SRAM is often corrupted by SEUs. 1 2 Two Honda Civics •Same year, same model, same colour, but are they•Of course not, and likewise, two chips have 3 Motivation •PUF: Physically Unclonable Function. •Process varia - Jun 00 7 6 Presidential Award for Faculty Excellence in Early Career Achievement Wright State University 04 7 Selected to become a Senior Member of the IEEE 04 TEACHING DISSERTATION/THESIS/ADVISING