Adaptive Test Optimization through Real Time Learning of Te - PowerPoint Presentation

Slide1

Adaptive Test Optimization through Real Time Learning of Test Effectiveness

ECE

7502 Class Discussion

Qing Qin

April 2, 2015Slide2

Requirements

Specification

Architecture

Logic / Circuits

Physical Design

Fabrication

Manufacturing Test

Packaging Test

PCB Test

System Test

PCB Architecture

PCB Circuits

PCB Physical Design

PCB Fabrication

Design and Test Development

Customer

Validate

Verify

Post Silicon Verification

Test

TestSlide3

What is Adaptive Testing?GRE or TOEFLGoal to maximize the precision of the exam

Select questions based on the examinee’s performance from previous questions

IC Testing

Goal to minimize the test time/costFor bad chips: Apply the most effective test patterns as early as possibleFor good

chips: Eliminate redundant test patterns3Slide4

Why Adaptive Testing?4

Large number of test patterns generated

Use of simplistic fault models for test generation

Inclusion of various test

types

R

edundant test patterns (70%-90%

)

At least 69% of 7,400 patterns not used during the production test of 500,000 Intel’s communication processor chips89% of useless patterns generated for stuck-at fault for testing 20,000 chips from IBMWant to identify and eliminate redundant patterns to reduce test costsSlide5

Paper Map5

[1]

Arslan

, B.; …”Adaptive Test Optimization through …," DATE’11.[2] Grady, M.

; …”Adaptive Testing – Cost Reduction through …" ITC’13.[3] Ferhani, F.; …”

How Many Test Patterns are Useless?” VTS’08. [4] Guo, R.; … ”Evaluation of Test Metrics …” VTS’06.

[5] Nigh, P.; … ”Test Method Evaluation Experiments & Data…,” ITC’00.

Opportunity to reduce test cost

[2] validates the effectiveness of a similar method in industry[1] proposes a framework for adaptive test optimization

[3] quantitatively predicts the number of useless patterns

[4] shows low correlation between test metrics and defect coverage

[5] reveals the existence of useless patterns

Test patterns must be actually applied to manufactured chips

Adaptive testing in use

Optimization space estimationSlide6

How to Identify Useless Patterns?

6

Want to identify

as early as possible

Traditionally, test pattern effectiveness analysis available only after the production test

Use test metrics, such as stuck-at coverage?

Test pattern set with high coverage == useful?

69% of 7,400 patterns are useless

99.5% of these useless patterns are required for obtaining stuck-at coverage greater than 85%Test patterns have to be actually applied to manufactured ICs to evaluate the effectiveness

Real-Time Learning & Adaptive Optimization!Slide7

Test Effectiveness LearningBenefits of Interactive Learning FrameworkApplying effective test patterns early and reducing average test time for defective chips

Pinpointing ineffective patterns at the end of sequence and introducing the possibility of eliminating the useless patterns

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[2]Slide8

Test Effectiveness LearningPolicy (π)

Detection Count Scoring

Detection Time Scoring

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[2]Slide9

Test Effectiveness Learningε-Greedy Ordering

9

[2]

Determine sample size of non-greedy and

ε

-greedy phase

Sort the test patterns randomly in the non-greedy phase

Sort based on scores with P=1-ε in the

ε

-greedy phase

Sort based on scores for all subsequent devicesSlide10

Experiment Results10

Defective Chips for Simulation

200,000 faults are selected from a sample set of most likely bridging faults and injected one at a time into a industrial design with 48,500 FF.

4,000 stuck-at vectors generated by an ATPG tool

4 Experiment Configurations

Configuration

Scoring Policy

Ordering Algorithm

1

Detection Count

Greedy

2

Detection Time

Greedy

3

Detection Count

ε

-Greedy

4

Detection Time

ε

-Greedy

Static

None

NoneSlide11

Experiment Results11

Goals

Confirm that reordering test patterns reduces test time

Select the most effective configuration

4

Experiment Configurations

Configuration

Scoring Policy

Ordering Algorithm

1

Detection Count

Greedy

2

Detection Time

Greedy

3

Detection Count

ε

-Greedy

4

Detection Time

ε

-Greedy

Static

None

NoneSlide12

Experiment Results12

Result: Test

time as test effectiveness is learned

[2]Slide13

Experiment ResultsResult: Test Time Improvement Over Static Test

4 Experiment Configurations

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Configuration

Scoring Policy

Ordering Algorithm

1

Detection Count

Greedy

2

Detection Time

Greedy

3

Detection Count

ε

-Greedy

4

Detection Time

ε

-Greedy

Static

None

None

[2]Slide14

Adaptive Test Pattern OptimizationWant to eliminate useless

test patterns to further decrease test time

Risky if defect behavior changes

For example, change from one wafer to anotherTest Pattern Order CorrelationCorrelation between the pattern orders at the beginning and the

and of a moving window of length, W_coefTo track the correlation changes between test patterns orders

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Adaptive Test Pattern OptimizationTest Pattern Elimination Criterion

A particular pattern is eliminated if the following is satisfied:

Defect Mechanism Shift Detection Criterion

All previously eliminated vectors are inserted back to the test flow if:

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Experiment ResultsResult: Test Pattern Order Convergence

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[2]Slide17

Experiment ResultsResult: Effect of Defect Behavior Change

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[2]Slide18

ConclusionsReduces the average test time to detect the defective devices by ordering vectors based on their effectiveness

Reduces the test time for all deices by exposing and eliminating the ineffective devices

Reduces the test cost and the test’s overall contribution to final product cost

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Discussion QuestionsWhat is your

o

verall reaction to the paper?

How does dropping part of the test patterns affect the escape rate?How can we adopt the method for chip testing in the lab?

19Slide20

Test Pattern Sampling in UseScore of Individual Failing Pattern on a Die:

Given

Running Average

Score for this Pattern for n Failing Dies:

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Test Pattern Sampling in UseFully test (not stop-at-first-failure) all bad die on one wafer and score all test patterns

From then on, reorder the test patterns and run half the patterns in the set

Every 5

th chip, run all the patterns to continue to collect score statisticsRestart the algorithm at the beginning of each wafer log

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Test Pattern Sampling in Use22

[1]Slide23

Escape RateProbability of Escape given by Hyper Geometric Distribution

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Escape Rate24

[1]Slide25

Papers[1] M.; Pepper, B.; Patch, J.;

Degregorio

, M.; Nigh, P., "Adaptive testing - Cost reduction through test pattern sampling,"

Test Conference (ITC), 2013 IEEE International , vol., no., pp.1,8, 6-13 Sept. 2013.[2] Arslan, B.; Orailoglu

, A., "Adaptive test optimization through real time learning of test effectiveness," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, vol., no., pp.1,6, 14-18, March 2011.[3] Ferhani, F.-F.; Saxena, N.R.; McCluskey

, E.J.; Nigh, P., "How Many Test Patterns are Useless?," VLSI Test Symposium, 2008. VTS 2008. 26th IEEE , vol., no., pp.23,28, April 27 2008-May 1 2008.[4] Guo, R.; Mitra

, S.; Amyeen, E.; Jinkyu Lee; Sivaraj, S.; Venkataraman, S., "Evaluation of test metrics: stuck-at, bridge coverage estimate and gate exhaustive," VLSI Test Symposium, 2006. Proceedings. 24th IEEE , vol., no., pp.6 pp.,71, April 30 2006-May 4 2006

.[5] Nigh, P.; Gattiker, A., "Test method evaluation experiments and data," Test Conference, 2000. Proceedings. International , vol., no., pp.454,463, 2000.

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