PPT-VHDL Discussion

Subprograms IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology 1 2 Subprograms A subprogram is an encapsulated sequence of sequential statements that define an algorithm The algorithm uses the values of input parameters passed to the subprogram when it is called to compute results or cause some desired effect The actual code for a subprogram appears only once in the text of a program However the subprogram can be executed by calling it from anywhere in the program . It can be used to check for design errors eg the product of two negative numbers should always result in a positive number and also to check for input or signal errors eg two signals should never be 1 at the same time For example say that the signal library ieee use ieeestdlogic1164all entity shift is portC SI in stdlogic SO out stdlogic end shift architecture archi of shift is signal tmp stdlogicvector7 downto 0 begin process C begin if Cevent and C1 then for i in 0 to 6 loop tmpi1 tmpi end Boolean Algebra and Reduction Techniques. 1. 5-9 . Karnaugh. Mapping. Used to minimize the number of gates. Reduce circuit cost. Reduce physical size. Reduce gate failures. Requires SOP form. Karnaugh. Andrey. . Kuyel. Supervised by . Mony. . Orbach. Spring 2011. Midterm Presentation (One . semestrial. project). High speed digital systems laboratory. High-Throughput FFT. Technion. . - Israel institute of technology. 367 – Logic Design. Module 3 – VHDL. Agenda. Hardware Description Languages. VHDL History. VHDL Systems and Signals. VHDL Entities, Architectures, and Packages. VHDL Data Types. VHDL Operators. VHDL Structural Design. orks ht 2013 S y nthWorks Desi g n Inc. orksCopyright Full . Adder . on the . Atlys. . Demo Board. Jeremy Sandoval. University of Washington . April 30, . 2013. 1. Last Week. Step-by-step instructions for implementing a four bit adder using previously written VHDL code. Nikhil Garrepalli. Fall 2012. (Refer to the comments if required). ELEC2200-002 Fall 2012, Sep 26. 1. (Adopted from Profs. Nelson and Stroud). HDLs in Digital System Design. Model and document digital systems. Examples taken from Ch. 4 of the Harris & Harris book 2. nd. Edition (recommended but not required book for this class). VHDL. Modules and Assign Statements. Slide derived from Harris & Harris book. Decoders. Introduction. A . decoder is a . multiple-input, multiple-output logic circ. uit that converts . coded . inputs . into coded outputs, where the input and output codes are different. . The input . Design. The Test Bench Concept. Project simulations. Behavioral/RTL – verify functionality. Model in VHDL/. Verilog. Drive with “force file” or . testbench. Post-Synthesis. Synthesized gate-level VHDL/. Lecture 18 SORTING in Hardware SSEG GPO2 Sorting Switches LED Buttons GPI2 Sorting - Required I nterface Sort Clock R eset n DataIn N DataOut N Done RAdd L WrInit S (0=initialization 1=computations) The Desired Brand Effect Stand Out in a Saturated Market with a Timeless Brand Some pictures are obtained from . FPGA Express V. HDL Reference Manual, it is accessible from the machines in the lab at /programs/Xilinx foundation series/VDHL reference manual. /programs/Xilinx foundation series/foundation project manager/foundation help content/XVDHL compiler help pages.