Lecture 18 SORTING in Hardware SSEG GPO2 Sorting Switches LED Buttons GPI2 Sorting Required I nterface Sort Clock R eset n DataIn N DataOut N Done RAdd L WrInit S 0initialization 1computations ID: 769690
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Lecture 18 SORTING in Hardware
SSEG GPO2 Sorting Switches LED Buttons GPI2
Sorting - Required I nterface Sort Clock R eset n DataIn N DataOut N Done RAdd L WrInit S (0=initialization 1=computations) Rd
Sorting - Required I nterface
Simulation results for the sort operation (1)Loading memory and starting sorting
Simulation results for the sort operation (2)Completing sorting and reading out memory
Before sorting During Sorting After sorting Address 0 1 2 3 3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2 4 4 4 4 4 4 4 3 1 1 1 1 2 2 3 4 i=0 i=0 i=0 i=1 i=1 i=2 j=1 j=2 j=3 j=2 j=3 j=3 M i M j Legend: position of memory indexed by i position of memory indexed by j Sorting - Example
Pseudocode for i = 0 to k 2 do A = ; for j = i + 1 to k 1 do B = M j ; if B < A then M i = B ; M j = A ; A = M i ; endif ; endfor; endfor; – - [load input data] wait for s=1 for i = 0 to 2 do A = M i ; for j = i + 1 to 3 do B = M j ; if B < A then M i = B ; M j = A ; A = M i ; endif ; endfor; endfor; [load input data] wait for s=1 Done wait for s=0 [read output data] go to the beginning FOR k = 4 FOR any k ≥ 2 M i Done wait for s=0 [read output data] go to the beginning
Pseudocode wait for s=1 for i=0 to k-2 do A = M i for j=i+1 to k-1 do B = Mj if A > B then M i = B M j = A A = Mi end if end for end forDonewait for s=0go to the beginning
Structure of a Typical Digital System Datapath ( Execution Unit ) Control ler (Control Unit ) Data Inputs Data Outputs Control Inputs Control Outputs Control Signals Status Signals
Hardware Design with RTL VHDL Pseudocode Datapath Control ler Block diagram ASM chart VHDL code VHDL code Interface
Text description Interface Pseudocode Block diagram of the Datapath Interface divided into the Datapath and ControllerASM chart of the ControllerRTL VHDL code of the Datapath, Controller, and Top-level Unit Testbench for the Datapath, Controller, and Top-Level Unit Functional simulation and debuggingIntegration with the FPro System HardwareSoftwareSynthesis and Implementation Experimental testing using FPGA board Steps of the Design Process 12
Contest for the Fastest Implementation of Sorting Bonus points will be awarded to students who perform sorting ( correctly ) using the smallest number of clock cycles in hardware and/or software Possible optimizations: Faster sorting algorithms in software Efficient C implementation Faster sorting algorithms in hardware Efficient VHDL implementation
SORTING solutions
Block diagram of the Datapath
DIN DOUT ADDR WE CLK EN CLK RST EN CLK RST A>B 0 1 s WrInit Clock Clock Clock Resetn Resetn Wr 1 0 Bout EA EB AgtB Addr s 0 1 0 1 DataIn RAdd Rd DataOut Csel LD CLK EN RST Resetn LD CLK EN RST Resetn Li Ei Clock Ej Lj Clock = k-2 = k-1 zi zj N L L L L N N N N N ABMux A B i j Mij Din We 0 L +1 Block diagram of the Datapath s 0 1
N Clock Resetn Data Out N WrInit s Done Wr Li Ei Lj Ej EA EB Bout Csel Datapath Controller RAddr L zi Interface with the division into the Datapath and Controller DataIn Rd AgtB zj
ASM Chart of the Controller
Timing Waveforms Explaining the Need for State S3