Computer Architecture Lecture 6b SoftMC Hasan Ibrahim Hasan ETH Zürich Fall 2018 4 October 2018 SoftMC A Flexible and Practical OpenSource Infrastructure for Enabling Experimental DRAM Studies ID: 765493
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Computer ArchitectureLecture 6b: SoftMC Hasan Ibrahim Hasan ETH Zürich Fall 2018 4 October 2018
SoftMC A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies Hasan Hassan , Nandita Vijaykumar, Samira Khan,Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu 2
Executive SummaryTwo critical problems of DRAM: Reliability and Performance Characterize , analyze, and understand DRAM cell behaviorWe design and implement SoftMC, an FPGA-based DRAM testing infrastructureFlexible and Easy to Use (C++ API)Open-source (github.com/CMU-SAFARI/ SoftMC)We implement two use casesA retention time distribution testAn experiment to validate two latency reduction mechanismsSoftMC enables a wide range of studies 3
Outline 4 DRAM Basics & Motivation SoftMC Use Cases Retention Time Distribution Study Evaluating Recently-Proposed Ideas Future Research Directions Conclusion
DRAM Operations 5 CPU Memory Controller DRAM Row Sense Amplifier Activate Read Precharge Memory Bus DRAM Cell
DRAM Latency 6 Activate time Read Precharge Activation Latency Ready-to-access Latency Precharge Latency Activate 0 (refresh) 64 ms DRAM Cell Sense Amplifier Retention Time: The interval during which the data is retained correctly in the DRAM cell without accessing it
Latency vs. Reliability 7 Activate time Read Precharge Activation Latency Ready-to-access Latency Precharge Latency Activate DRAM Cell Sense Amplifier Violating latencies negatively affects DRAM reliability
Other Factors Affecting Reliability and LatencyTemperatureVoltageInter-cell InterferenceManufacturing ProcessRetention Time… 8 To develop new mechanisms improving reliability and latency, we need to better understand the effects of these factors
Characterizing DRAMMany of the factors affecting DRAM reliability and latency cannot be properly modeled9 We need to perform experimental studies of real DRAM chips
Outline 10 DRAM Basics & Motivation SoftMC Use Cases Retention Time Distribution Study Evaluating Recently-Proposed Ideas Future Research Directions Conclusion
Goals of a DRAM Testing InfrastructureFlexibilityAbility to test any DRAM operationAbility to test any combination of DRAM operations and custom timing parametersEase of useSimple programming interface (C++)Minimal programming effort and timeAccessible to a wide range of userswho may lack experience in hardware design 11
SoftMC: High-level View 12 FPGA-based memory characterization infrastructure Prototype using Xilinx ML605 Easily programmable using the C++ API
SoftMC: Key Components13 1. SoftMC API 2. PCIe Driver3. SoftMC Hardware
SoftMC API InstructionSequence iseq ; iseq.insert ( genACT (bank, row)); iseq.insert ( genWAIT ( tRCD )); iseq.insert ( genWR (bank, col, data)); iseq.insert ( genWAIT ( tCL + tBL + tWR )); iseq.insert ( genPRE (bank)); iseq.insert ( genWAIT ( tRP )); iseq.insert ( genEND ()); iseq.execute ( fpga ); 14 Writing data to DRAM: Instruction generator functions
SoftMC: Key Components15 1. SoftMC API 2. PCIe Driver*3. SoftMC Hardware Communicates raw data with the FPGA * Jacobsen, Matthew, et al. "RIFFA 2.1: A reusable integration framework for FPGA accelerators." TRETS, 2015
SoftMC Hardware 16 PCIe ControllerInstruction Receiver Instruction Queue Instruction Dispatcher DDR PHY Auto-refresh Controller Calibration Controller Read Capture SoftMC Hardware (FPGA) Instructions Activate Read Wait (Ready-to-access Latency) Data Host Machine DRAM
Outline 17 DRAM Basics & Motivation SoftMC Use Cases Retention Time Distribution Study Evaluating Recently-Proposed Ideas Future Research Directions Conclusion
Retention Time Distribution Study18 Increase the refresh interval Observe Errors Read Back Wait (Refresh Interval) Write Reference Data to a Row Can be implemented with just ~100 lines of code
Retention Time Test: Results19 @ ~20 ⁰ C (room temperature) Module AModule B Module C Validates the correctness of the SoftMC Infrastructure
Outline 20 DRAM Basics & Motivation SoftMC Use Cases Retention Time Distribution Study Evaluating Recently-Proposed Ideas Future Research Directions Conclusion
Accessing Highly-charged Cells Faster21NUAT (Shin+, HPCA 2014) ChargeCache (Hassan+, HPCA 2016)A highly-charged cell can be accessed with low latency
How a Highly-Charged Cell Is Accessed Faster? 22 Activate DRAM Cell Sense Amplifier time Read Precharge Activation Latency Ready-to-access Latency Precharge Latency Activate 0 (refresh) 64 ms
Ready-to-access Latency Test23 Change the Wait Interval Observe ErrorsRead Back Wait for the Wait Interval Write Reference Data Longer wait Shorter wait Higher cell charge Lower cell charge With custom ready-to-access latency parameter Can be implemented with just ~150 lines of code
Ready-to-access Latency: Results24 @ 80 ⁰ C temperatureReal Curves We d o not observe the expected latency reduction effect in existing DRAM chips Expected Curves
Why Don’t We See the Latency Reduction Effect?The memory controller cannot externally control when a sense amplifier gets enabled in existing DRAM chips 25 Data 0 Data 1 Cell time charge Sense Amp R/W ACT Ready to Access Charge Level Ready to Access Fixed Latency! Enabling the Sense Amplifier Potential Reduction
Outline 26 DRAM Basics & Motivation SoftMC Use Cases Retention Time Distribution Study Evaluating Recently-Proposed Ideas Future Research Directions Conclusion
Future Research DirectionsMore Characterization of DRAMHow are the cell characteristics changing with different generations of technology nodes?What types of usage accelerate aging ?Characterization of Non-volatile MemoryExtensionsMemory SchedulingWorkload AnalysisTestbed for in-memory Computation27
Outline 28 DRAM Basics & Motivation SoftMC Use Cases Retention Time Distribution Study Evaluating Recently-Proposed Ideas Future Research Directions Conclusion
ConclusionSoftMC: First publicly-available FPGA-based DRAM testing infrastructureFlexible and Easy to Use Implemented two use cases Retention Time Distribution StudyEvaluation of two recently-proposed latency reduction mechanismsSoftMC can enable many other studies, ideas, and methodologies in the design of future memory systemsDownload our prototype29 github.com/CMU-SAFARI/SoftMC
SoftMC A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies Hasan Hassan , Nandita Vijaykumar, Samira Khan,Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu 30
Backup Slides31
Key SoftMC Instructions32
SoftMC @ Github33
Ready-to-Access Latency Test Results34 Module A Module C Module B
Activation Latency Test35 Change the wait interval Observe Errors ACT-PRE Wait for the Wait Interval Write Reference Data With low activation latency parameter Wait for the Wait Interval Read Back
Activation Latency Test Results36 Module A Module C Module B