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 Copyright © 2019, Elsevier Inc. All rights reserved.  Copyright © 2019, Elsevier Inc. All rights reserved.

Copyright © 2019, Elsevier Inc. All rights reserved. - PowerPoint Presentation

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Copyright © 2019, Elsevier Inc. All rights reserved. - PPT Presentation

Chapter 1 Fundamentals of Quantitative Design and Analysis Computer Architecture A Quantitative Approach Sixth Edition Computer Technology Performance improvements Improvements in semiconductor technology ID: 776392

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Presentation Transcript

Slide1

Copyright © 2019, Elsevier Inc. All rights reserved.

Chapter 1

Fundamentals of Quantitative Design and Analysis

Computer Architecture

A Quantitative Approach

, Sixth Edition

Slide2

Computer Technology

Performance improvements:Improvements in semiconductor technologyFeature size, clock speedImprovements in computer architecturesEnabled by HLL compilers, UNIXLead to RISC architecturesTogether have enabled:Lightweight computersProductivity-based managed/interpreted programming languages

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Introduction

Slide3

Single Processor Performance

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Introduction

Slide4

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Current Trends in Architecture

Cannot continue to leverage Instruction-Level parallelism (ILP)Single processor performance improvement ended in 2003New models for performance:Data-level parallelism (DLP)Thread-level parallelism (TLP)Request-level parallelism (RLP)These require explicit restructuring of the application

Introduction

Slide5

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Classes of Computers

Personal Mobile Device (PMD)e.g. start phones, tablet computersEmphasis on energy efficiency and real-timeDesktop ComputingEmphasis on price-performanceServersEmphasis on availability, scalability, throughputClusters / Warehouse Scale ComputersUsed for “Software as a Service (SaaS)”Emphasis on availability and price-performanceSub-class: Supercomputers, emphasis: floating-point performance and fast internal networksInternet of Things/Embedded ComputersEmphasis: price

Classes of Computers

Slide6

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Parallelism

Classes of parallelism in applications:Data-Level Parallelism (DLP)Task-Level Parallelism (TLP)Classes of architectural parallelism:Instruction-Level Parallelism (ILP)Vector architectures/Graphic Processor Units (GPUs)Thread-Level ParallelismRequest-Level Parallelism

Classes of Computers

Slide7

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Flynn’s Taxonomy

Single instruction stream, single data stream (SISD)Single instruction stream, multiple data streams (SIMD)Vector architecturesMultimedia extensionsGraphics processor unitsMultiple instruction streams, single data stream (MISD)No commercial implementationMultiple instruction streams, multiple data streams (MIMD)Tightly-coupled MIMDLoosely-coupled MIMD

Classes of Computers

Slide8

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Defining Computer Architecture

“Old” view of computer architecture:Instruction Set Architecture (ISA) designi.e. decisions regarding:registers, memory addressing, addressing modes, instruction operands, available operations, control flow instructions, instruction encoding“Real” computer architecture:Specific requirements of the target machineDesign to maximize performance within constraints: cost, power, and availabilityIncludes ISA, microarchitecture, hardware

Defining Computer Architecture

Slide9

Instruction Set Architecture

Class of ISAGeneral-purpose registersRegister-memory vs load-storeRISC-V registers32 g.p., 32 f.p.

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Defining Computer Architecture

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Slide10

Instruction Set Architecture

Memory addressingRISC-V: byte addressed, aligned accesses fasterAddressing modesRISC-V: Register, immediate, displacement (base+offset)Other examples: autoincrement, indexed, PC-relativeTypes and size of operandsRISC-V: 8-bit, 32-bit, 64-bit

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Defining Computer Architecture

Slide11

Instruction Set Architecture

OperationsRISC-V: data transfer, arithmetic, logical, control, floating pointSee Fig. 1.5 in textControl flow instructionsUse content of registers (RISC-V) vs. status bits (x86, ARMv7, ARMv8)Return address in register (RISC-V, ARMv7, ARMv8) vs. on stack (x86)EncodingFixed (RISC-V, ARMv7/v8 except compact instruction set) vs. variable length (x86)

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Defining Computer Architecture

Slide12

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Trends in Technology

Integrated circuit technology (Moore’s Law)Transistor density: 35%/yearDie size: 10-20%/yearIntegration overall: 40-55%/yearDRAM capacity: 25-40%/year (slowing)8 Gb (2014), 16 Gb (2019), possibly no 32 GbFlash capacity: 50-60%/year8-10X cheaper/bit than DRAMMagnetic disk capacity: recently slowed to 5%/yearDensity increases may no longer be possible, maybe increase from 7 to 9 platters8-10X cheaper/bit then Flash200-300X cheaper/bit than DRAM

Trends in Technology

Slide13

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Bandwidth and Latency

Bandwidth or throughputTotal work done in a given time32,000-40,000X improvement for processors300-1200X improvement for memory and disksLatency or response timeTime between start and completion of an event50-90X improvement for processors6-8X improvement for memory and disks

Trends in Technology

Slide14

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Bandwidth and Latency

Log-log plot of bandwidth and latency milestones

Trends in Technology

Slide15

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Transistors and Wires

Feature sizeMinimum size of transistor or wire in x or y dimension10 microns in 1971 to .011 microns in 2017Transistor performance scales linearlyWire delay does not improve with feature size!Integration density scales quadratically

Trends in Technology

Slide16

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Power and Energy

Problem: Get power in, get power outThermal Design Power (TDP)Characterizes sustained power consumptionUsed as target for power supply and cooling systemLower than peak power (1.5X higher), higher than average power consumptionClock rate can be reduced dynamically to limit power consumptionEnergy per task is often a better measurement

Trends in Power and Energy

Slide17

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Dynamic Energy and Power

Dynamic energyTransistor switch from 0 -> 1 or 1 -> 0½ x Capacitive load x Voltage2Dynamic power½ x Capacitive load x Voltage2 x Frequency switchedReducing clock rate reduces power, not energy

Trends in Power and Energy

Slide18

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Power

Intel 80386 consumed ~ 2 W3.3 GHz Intel Core i7 consumes 130 WHeat must be dissipated from 1.5 x 1.5 cm chipThis is the limit of what can be cooled by air

Trends in Power and Energy

Slide19

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Reducing Power

Techniques for reducing power:Do nothing wellDynamic Voltage-Frequency ScalingLow power state for DRAM, disksOverclocking, turning off cores

Trends in Power and Energy

Slide20

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Static Power

Static power consumption25-50% of total powerCurrentstatic x VoltageScales with number of transistorsTo reduce: power gating

Trends in Power and Energy

Slide21

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Trends in Cost

Cost driven down by learning curveYieldDRAM: price closely tracks costMicroprocessors: price depends on volume10% less for each doubling of volume

Trends in Cost

Slide22

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Integrated Circuit Cost

Integrated circuitBose-Einstein formula:Defects per unit area = 0.016-0.057 defects per square cm (2010)N = process-complexity factor = 11.5-15.5 (40 nm, 2010)

Trends in Cost

Slide23

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Dependability

Module reliabilityMean time to failure (MTTF)Mean time to repair (MTTR)Mean time between failures (MTBF) = MTTF + MTTRAvailability = MTTF / MTBF

Dependability

Slide24

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Measuring Performance

Typical performance metrics:Response timeThroughputSpeedup of X relative to YExecution timeY / Execution timeXExecution timeWall clock time: includes all system overheadsCPU time: only computation timeBenchmarksKernels (e.g. matrix multiply)Toy programs (e.g. sorting)Synthetic benchmarks (e.g. Dhrystone)Benchmark suites (e.g. SPEC06fp, TPC-C)

Measuring Performance

Slide25

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Principles of Computer Design

Take Advantage of Parallelisme.g. multiple processors, disks, memory banks, pipelining, multiple functional unitsPrinciple of LocalityReuse of data and instructionsFocus on the Common CaseAmdahl’s Law

Principles

Slide26

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Principles of Computer Design

The Processor Performance Equation

Principles

Slide27

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Principles of Computer Design

Principles

Different instruction types having different CPIs

Slide28

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Principles of Computer Design

Principles

Different instruction types having different CPIs

Slide29

Fallacies and Pitfalls

All exponential laws must come to an endDennard scaling (constant power density)Stopped by threshold voltageDisk capacity30-100% per year to 5% per yearMoore’s LawMost visible with DRAM capacityITRS disbandedOnly four foundries left producing state-of-the-art logic chips11 nm, 3 nm might be the limit

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Slide30

Fallacies and Pitfalls

Microprocessors are a silver bulletPerformance is now a programmer’s burdenFalling prey to Amdahl’s LawA single point of failureHardware enhancements that increase performance also improve energy efficiency, or are at worst energy neutralBenchmarks remain valid indefinitelyCompiler optimizations target benchmarks

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Slide31

Fallacies and Pitfalls

The rated mean time to failure of disks is 1,200,000 hours or almost 140 years, so disks practically never failMTTF value from manufacturers assume regular replacementPeak performance tracks observed performanceFault detection can lower availabilityNot all operations are needed for correct execution

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