PPT-1 Scalable Transactional Memory Scheduling

Gokarna Sharma A joint work with Costas Busch Louisiana State University Agenda Introduction and Motivation Scheduling Bounds in Different Software Transactional Memory Implementations TightlyCoupled Shared Memory Systems. Gokarna. Sharma. Costas Busch. Louisiana State University, USA. WTTM 2010 - 2nd Workshop on the Theory of Transactional Memory. 1. TexPoint fonts used in EMF. . Read the TexPoint manual before you delete this box.: . Memory. Supporting Large Transactions. Anvesh. . Komuravelli. Abe Othman. Kanat. . Tangwongsan. Hardware-based. . Concurrent Programs. obj.x. = 7;. find_primes. ();. // intrusion test. if (. obj.x. Rajwar. , R., . Herlihy. , M., and Lai, K. 2005. presented by . VasilyVolkov. , 04/30/08. Motivation. Transactional Memory is good. Never deadlocks. Makes concurrent programming easier. But requires programmer to be aware of. T. Rogers, M O’Conner, and T. . Aamodt. MICRO 2012. Goal. Understand the relationship between schedulers (warp/wavefront) and locality behaviors . Distinguish between inter-wavefront and intra-wavefront locality. Maurice Herlihy (DEC), J. Eliot & B. Moss (UMass). Presenter: Mariano Diaz. CS 5204 – Fall, 2009. Part 1: Concepts and Hardware-based Approaches. Introduction. What’s a transaction?. Transaction: a finite sequence of machine instructions, executed by a single process, that satisfies the following:. Processors. Presented by . Remzi. Can . Aksoy. *Some slides . are. . borrowed from a ‘Papers We Love’ . Presentation. EECS 582 – F16. 1. Outline. The . Scalable Commutativity Rule: . Whenever interface operations commute, they can be implemented in a way that scales. Luis . Herranz. Arribas. Supervisor: Dr. José M. Martínez Sánchez. Video Processing and Understanding Lab. Universidad . Aut. ónoma. de Madrid. Outline. Introduction. Integrated. . summarization. Prof. Smruti R. Sarangi. IIT Delhi. Outline. Multicore Processors. Parallel Programming Pardigms. Transactional Memory: Basics. Software Transactional Memory(STM). Hardware Transactional Memory. Multicores in the last Five Years. T. Rogers, M O’Conner, and T. . Aamodt. MICRO 2012. Goal. Understand the relationship between schedulers (warp/wavefront) and locality behaviors . Distinguish between inter-wavefront and intra-wavefront locality. Burst Buffer Enabled HPC Clusters. Chunxiao. Liao. 1. Background. High performance storage is critical to achieving computational efficiency on high performance computing (HPC) systems. . Capacity growth of disks continues to outpace increases in their bandwidth. Bulk-synchronous Programming Models on. CPU Architectures. Hee-Seok. Kim. , . Izzat. El Hajj, John Stratton,. Steven . Lumetta. and . Wen-mei. . Hwu. CPU. (Intel, AMD, PowerPC). GPU. (NVIDIA, AMD, Imagination, ARM). Larry Peterson. In collaboration with . Arizona. , Akamai. ,. . Internet2. , NSF. , North Carolina, . Open Networking Lab, Princeton. (and several pilot sites). S3. DropBox. GenBank. iPlant. Data Management Challenge. Alvaro Moreira & Luigi Carro. Instituto de Informática – UFRGS . Brasil. 1. Outline – Part III. Work . done at UFRGS on . detection/correction . of . Control Flow Errors (CFEs) with LLVM. Similarities and differences with Security. Large scale computing systems. Scalability . issues. Low level and high level communication abstractions in scalable systems. Network interface . Common techniques for high performance communication.