PPT-1 Scalable Transactional Memory Scheduling

Gokarna Sharma A joint work with Costas Busch Louisiana State University Agenda Introduction and Motivation Scheduling Bounds in Different Software Transactional Memory Implementations TightlyCoupled Shared Memory Systems. tumde Abstract So far transactional memoryalthough a promising techniquesuffered from the absence of an ef64257cient hardware implementation The upcoming Haswell microarchitecture from Intel introduces hardware transactional memory HTM in mainstream FernandesJoaoCachopo istutlpt Abstract Software Transactional Memory STM was initially propose d as a lockfree mechanism for concurrency control Early imple menta tions had ef64257ciency limitations and soon obstructionfre e propos als appeared to ta Gokarna. Sharma. Costas Busch. Louisiana State University, USA. WTTM 2010 - 2nd Workshop on the Theory of Transactional Memory. 1. TexPoint fonts used in EMF. . Read the TexPoint manual before you delete this box.: . Memory. Supporting Large Transactions. Anvesh. . Komuravelli. Abe Othman. Kanat. . Tangwongsan. Hardware-based. . Concurrent Programs. obj.x. = 7;. find_primes. ();. // intrusion test. if (. obj.x. Rajwar. , R., . Herlihy. , M., and Lai, K. 2005. presented by . VasilyVolkov. , 04/30/08. Motivation. Transactional Memory is good. Never deadlocks. Makes concurrent programming easier. But requires programmer to be aware of. Patrick Santos (4465359). 1. Agenda. What is transactional memory (TM)?. Example transactions. Deadlocks and Cache Coherence. Types of TM. Implementations . & proposals . in industry. Sun / Oracle. Maurice Herlihy (DEC), J. Eliot & B. Moss (UMass). Presenter: Mariano Diaz. CS 5204 – Fall, 2009. Part 1: Concepts and Hardware-based Approaches. Introduction. What’s a transaction?. Transaction: a finite sequence of machine instructions, executed by a single process, that satisfies the following:. Prof. Smruti R. Sarangi. IIT Delhi. Outline. Multicore Processors. Parallel Programming Pardigms. Transactional Memory: Basics. Software Transactional Memory(STM). Hardware Transactional Memory. Multicores in the last Five Years. Burst Buffer Enabled HPC Clusters. Chunxiao. Liao. 1. Background. High performance storage is critical to achieving computational efficiency on high performance computing (HPC) systems. . Capacity growth of disks continues to outpace increases in their bandwidth. Prof. Smruti R. Sarangi. IIT Delhi. Outline. Multicore Processors. Parallel Programming Pardigms. Transactional Memory: Basics. Software Transactional Memory(STM). Hardware Transactional Memory. Multicores in the last Five Years. Operational & Analytical Database. Ricardo Jimenez-Peris. LeanXcale . CEO & . Founder. LeanXcale. New database vendor. Result of leading edge research in:. Scalable transactional management. Scalable data management. Alvaro Moreira & Luigi Carro. Instituto de Informática – UFRGS . Brasil. 1. Outline – Part III. Work . done at UFRGS on . detection/correction . of . Control Flow Errors (CFEs) with LLVM. Similarities and differences with Security. Yoongu. Kim. Dongsu. Han. Onur Mutlu. Mor. . Harchol-Balter. Motivation. Modern multi-core systems . employ multiple memory controllers. Applications contend . with . each other in multiple controllers. Large scale computing systems. Scalability . issues. Low level and high level communication abstractions in scalable systems. Network interface . Common techniques for high performance communication.