SLVSB  NOVEMBER   REVISED AUGUST  POST OFFICE BOX  DALLAS TEXAS  Floating Bootstrap or GroundReference HighSide Driver Adaptive DeadTime Control ns Max RiseFall Times With
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SLVSB NOVEMBER REVISED AUGUST POST OFFICE BOX DALLAS TEXAS Floating Bootstrap or GroundReference HighSide Driver Adaptive DeadTime Control ns Max RiseFall Times With

3nF Load 24A Typical Output Current 45V to 15V Supply Voltage Range TTLCompatible Inputs Internal Schottky Bootstrap Diode Low Supply Current3 mA Typical Ideal for HighCurrent Single or Multiphase Power Supplies 872240 C to 125 C Operating Virtual Ju

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SLVSB NOVEMBER REVISED AUGUST POST OFFICE BOX DALLAS TEXAS Floating Bootstrap or GroundReference HighSide Driver Adaptive DeadTime Control ns Max RiseFall Times With




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Presentation on theme: "SLVSB NOVEMBER REVISED AUGUST POST OFFICE BOX DALLAS TEXAS Floating Bootstrap or GroundReference HighSide Driver Adaptive DeadTime Control ns Max RiseFall Times With"— Presentation transcript:


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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Floating Bootstrap or Ground-Reference High-Side Driver Adaptive Dead-Time Control 50-ns Max Rise/Fall Times With 3.3-nF Load 2.4-A Typical Output Current 4.5-V to 15-V Supply Voltage Range TTL-Compatible Inputs Internal Schottky Bootstrap Diode Low Supply Current....3 mA Typical Ideal for High-Current Single or Multiphase Power Supplies −40 C to 125 C Operating Virtual Junction-Temperature Range description The TPS2836 and TPS2837 are MOSFET drivers for synchronous-buck

power stages. These devices are ideal for designing a high-performance power supply using switching controllers that do not have MOSFET drivers. The drivers are designed to deliver minimum 2-A peak currents into large capacitive loads. The high-side driver can be configured as ground-reference or as floating-bootstrap. An adaptive dead-time control circuit eliminates shoot-through currents through the main power FETs during switching transitions and provides high ef ficiency for the buck regulator. The TPS2836 has a noninverting input, while the TPS2837 has an inverting input. These drivers,

available in 8-terminal SOIC packages, operate over a junction temperature range of − 40 C to 125 C. AVAILABLE OPTIONS PACKAGED DEVICES SOIC (D) −40 C to 125 TPS2836D TPS2837D The D package is available taped and reeled. Add R suffix to device type (e.g., TPS2836DR) Related Synchronous MOS FET Drivers DEVICE NAME ADDITIONAL FEATURES INPUTS TPS2830 ENABLE, SYNC and CROWBAR CMOS Noninverted TPS2831 ENABLE, SYNC and CROWBAR CMOS Inverted TPS2832 W/O ENABLE, SYNC and CROWBAR CMOS Noninverted TPS2833 W/O ENABLE, SYNC and CROWBAR CMOS Inverted TPS2834 ENABLE, SYNC and CROWBAR TTL

Noninverted TPS2835 ENABLE, SYNC and CROWBAR TTL Inverted Copyright 2002, Texas Instruments Incorporated !"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. Please be aware that an important notice concerning

avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D PACKAGE (TOP VIEW) IN PGND DT CC BOOT HIGHDR BOOTLO LOWDR
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 functional block diagram DT IN CC LOWDR BOOTLO HIGHDR BOOT PGND CC (TPS2836 Only) (TPS2837 Only) 1 M 250 k 250 k Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION BOOT Bootstrap terminal. A ceramic capacitor is connected between

BOOT and BOOTLO to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 F and 1 F. BOOTLO This terminal connects to the junction of the high-side and low-side MOSFETs. DT Dead-time control terminal. Connect DT to the junction of the high-side and low-side MOSFETs HIGHDR Output drive for the high-side power MOSFET IN Input signal to the MOSFET drivers (noninverting input for the TPS2836; inverting input for the TPS2837). LOWDR Output drive for the low-side power MOSFET PGND Power ground. Connect to the FET power ground. CC Input supply.

Recommended that a 1 F capacitor be connected from V CC to PGND.
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 detailed description low-side driver The low-side driver is designed to drive low r DS(on) N-channel MOSFETs. The current rating of the driver is 2 A, source and sink. high-side driver The high-side driver is designed to drive low r DS(on) N-channel MOSFET s. The current rating of the driver is 2 A, source and sink. The high-side driver can be configured as a ground-reference driver or a floating bootstrap

driver. The internal bootstrap diode is a Schottky for improved drive ef ficiency. The maximum voltage that can be applied between the BOOT terminal and ground is 30 V. dead-time (DT) control Dead-time control prevents shoot-through current from flowing through the main power FETs during switching transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until the voltage at the junction of the power FETs (Vdrain) is low; the

TTL-compatible DT terminal connects to the junction of the power FETs. IN The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The TPS2836 has a noninverting input; the TPS2837 has an inverting input. absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, V CC (see Note 1) −0.3 V to 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range: BOOT to PGND (high-side driver ON) −0.3 V to 30 V . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . BOOTLO to PGND −0.3 V to 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BOOT to BOOTLO −0.3 V to 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IN −0.3 V to 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DT −0.3 V to 30 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power

dissipation See Dissipation Rating Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating virtual junction temperature range, T −40 C to 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, T stg −65 C to 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260 . . . . . . . . . . . . . . . . . . . . . . . Stresses beyond those listed under “absolute maximum ratings” may

cause permanent damage to the device. These are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Unless otherwise specified, all voltages are with respect to PGND. DISSIPATION RATING TABLE PACKAGE 25 POWER RATING DERATING FACTOR ABOVE T = 25 = 70 POWER RATING = 85 POWER RATING 600 mW 6.0 mW/ 330 mW 240 mW recommended operating conditions MIN NOM MAX UNIT Supply

voltage, V CC 4.5 15 Input voltage BOOT to PGND 4.5 28
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 electrical characteristics over recommended operating virtual junction temperature range, CC = 6.5 V, C = 3.3 nF (unless otherwise noted) supply current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply voltage range 4.5 15 Quiescent current CC =15 V, V (ENABLE) = LOW 100 CC Quiescent current CC =15 V, V (ENABLE) = HIGH 300 400 CC Quiescent current CC =12 V, SWX = 200 kHz, HIGHDR = 50 pF, BOOTLO grounded, LOWDR = 50 pF,

See Note 2 mA NOTE 2: Ensured by design, not production tested. output drivers PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-side sink Duty cycle < 2%, BOOT – V BOOTLO = 4.5 V, V HIGHDR = 4 V 0.7 1.1 High-side sink (see Note 4) Duty cycle < 2%, pw < 100 (see Note 3) BOOT – V BOOTLO = 6.5 V, V HIGHDR = 5 V 1.1 1.5 (see Note 4) pw < 100 (see Note 3) BOOT – V BOOTLO = 12 V, V HIGHDR = 10.5 V 2.4 High-side Duty cycle < 2%, BOOT – V BOOTLO = 4.5 V, V HIGHDR = 0.5V 1.2 1.4 High-side source (see Note 4) Duty cycle < 2%, pw < 100 (see Note 3) BOOT – V BOOTLO = 6.5 V, V HIGHDR = 1.5 V 1.3 1.6 Peak

output- source (see Note 4) pw < 100 (see Note 3) BOOT – V BOOTLO = 12 V, V HIGHDR = 1.5 V 2.3 2.7 Peak output- current Low-side sink Duty cycle < 2%, CC = 4.5 V, V LOWDR = 4 V 1.3 1.8 current Low-side sink (see Note 4) Duty cycle < 2%, pw < 100 (see Note 3) CC = 6.5 V, V LOWDR = 5 V 2.5 (see Note 4) pw < 100 (see Note 3) CC = 12 V, V LOWDR = 10.5 V 3.5 Low-side Duty cycle < 2%, CC = 4.5 V, V LOWDR = 0.5V 1.4 1.7 Low-side source (see Note 4) Duty cycle < 2%, pw < 100 (see Note 3) CC = 6.5 V, V LOWDR = 1.5 V 2.4 source (see Note 4) pw < 100 (see Note 3) CC = 12 V, V LOWDR = 1.5 V 2.5 BOOT – V

BOOTLO = 4.5 V, V HIGHDR = 0.5 V High-side sink (see Note 4) BOOT – V BOOTLO = 6.5 V, V HIGHDR = 0.5 V High-side sink (see Note 4) BOOT – V BOOTLO = 12 V, V HIGHDR = 0.5 V BOOT – V BOOTLO = 4.5 V, V HIGHDR = 4 V 75 High-side source (see Note 4) BOOT – V BOOTLO = 6.5 V, V HIGHDR = 6 V 75 Output High-side source (see Note 4) BOOT – V BOOTLO = 12 V, V HIGHDR =11.5 V 75 Output resistance DRV = 4.5 V, V LOWDR = 0.5 V resistance Low-side sink (see Note 4) DRV = 6.5 V V LOWDR = 0.5 V 7.5 Low-side sink (see Note 4) DRV = 12 V, V LOWDR = 0.5 V DRV = 4.5 V, V LOWDR = 4 V 75 Low-side source (see Note 4)

DRV = 6.5 V, V LOWDR = 6 V 75 Low-side source (see Note 4) DRV = 12 V, V LOWDR = 11.5 V 75 NOTES: 3. Ensured by design, not production tested. 4. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the r DS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 POST OFFICE BOX 655303

DALLAS, TEXAS 75265 electrical characteristics over recommended operating virtual junction temperature range, CC = 6.5 V, C = 3.3 nF (unless otherwise noted) (continued) dead-time PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IH High-level input voltage LOWDR Over the V CC range (see Note 3) 0.7V CC IL Low-level input voltage LOWDR Over the V CC range (see Note 3) IH High-level input voltage DT Over the V CC range IL Low-level input voltage DT Over the V CC range NOTE 3: Ensured by design, not production tested. digital control terminals (IN) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IH

High-level input voltage Over the V CC range IL Low-level input voltage Over the V CC range switching characteristics over recommended operating virtual junction temperature range, = 3.3 nF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BOOT = 4.5 V, V BOOTLO = 0 V 60 HIGHDR output (see Note 3) BOOT = 6.5 V, V BOOTLO = 0 V 50 ns Rise time HIGHDR output (see Note 3) BOOT = 12 V, V BOOTLO = 0 V 50 ns Rise time CC = 4.5 V 40 LOWDR output (see Note 3) CC = 6.5 V 30 ns LOWDR output (see Note 3) CC = 12 V 30 ns BOOT = 4.5 V, V BOOTLO = 0 V 50 HIGHDR output (see Note 3) BOOT =

6.5 V, V BOOTLO = 0 V 40 ns Fall time HIGHDR output (see Note 3) BOOT = 12 V, V BOOTLO = 0 V 40 ns Fall time CC = 4.5 V 40 LOWDR output (see Note 3) CC = 6.5 V 30 ns LOWDR output (see Note 3) CC = 12 V 30 ns HIGHDR going low (excluding dead- BOOT = 4.5 V, V BOOTLO = 0 V 95 HIGHDR going low (excluding dead time) (see Note 3) BOOT = 6.5 V, V BOOTLO = 0 V 80 ns Propagation delay time time) (see Note 3) BOOT = 12 V, V BOOTLO = 0 V 65 ns Propagation delay time LOWDR going high (excluding BOOT = 4.5 V, V BOOTLO = 0 V 80 LOWDR going high (excluding dead-time) (see Note 3) BOOT = 6.5 V, V BOOTLO = 0 V

70 ns dead-time) (see Note 3) BOOT = 12 V, V BOOTLO = 0 V 60 ns LOWDR going low (excluding dead- CC = 4.5 V 80 Propagation delay time LOWDR going low (excluding dead- time) (see Note 3) CC = 6.5 V 70 ns Propagation delay time time) (see Note 3) CC = 12 V 60 ns DT to LOWDR and LOWDR to CC = 4.5 V 40 170 Driver nonoverlap time DT to LOWDR and LOWDR to HIGHDR (see Note 3) CC = 6.5 V 25 135 ns Driver nonoverlap time HIGHDR (see Note 3) CC = 12 V 15 85 ns NOTE 3: Ensured by design, not production tested.
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 POST OFFICE BOX

655303 DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 1 10 46 810 15 RISE TIME vs SUPPLY VOLTAGE 50 13 CC − Supply Voltage − V 35 40 45 20 25 30 − Rise Time − ns 57 91112 Low Side High Side = 3.3 nF = 25 15 14 Figure 2 FALL TIME vs SUPPLY VOLTAGE − Fall Time − ns 10 46 810 15 50 13 CC − Supply Voltage − V 35 40 45 20 25 30 57 91112 Low Side High Side = 3.3 nF = 25 15 14 Figure 3 RISE TIME vs JUNCTION TEMPERATURE − Rise Time − ns − Junction Temperature 10 0 50 100 15 50 125 35 40 45 20 25 30 25 75 −50 −25 CC = 6.5

V = 3.3 nF Low Side High Side Figure 4 FALL TIME vs JUNCTION TEMPERATURE − Fall Time − ns − Junction Temperature 10 0 50 100 15 50 125 35 40 45 20 25 30 25 75 Low Side High Side CC = 6.5 V = 3.3 nF −50 −25
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 5 20 46 810 30 LOW-TO-HIGH PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, LOW TO HIGH LEVEL 150 13 CC − Supply Voltage − V 70 80 90 40 50 60 57 91112 120 130 140 100 110 Low Side PLH − Low-to-High

Propagation Delay Time − ns = 3.3 nF = 25 15 14 Figure 6 HIGH-TO-LOW PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, HIGH TO LOW LEVEL CC − Supply Voltage − V 20 46 810 30 150 13 70 80 90 40 50 60 57 91112 120 130 140 100 110 Low Side PHL − High-to-Low Propagation Delay Time − ns = 3.3 nF = 25 15 14 High Side Figure 7 LOW-TO-HIGH PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE − Junction Temperature 20 0 50 100 30 150 125 70 80 90 40 50 60 25 75 120 130 140 100 110 PLH − Low-to-High Propagation Delay Time − ns −25 −50 CC = 6.5 V = 3.3 nF

High Side Low Side Figure 8 HIGH-TO-LOW PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE − Junction Temperature 20 0 50 100 30 150 125 70 80 90 40 50 60 25 75 120 130 140 100 110 PHL − High-to-Low Propagation Delay Time − ns Low Side High Side CC = 6.5 V = 3.3 nF −25 −50
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 9 DRIVER-OUTPUT RISE TIME vs LOAD CAPACITANCE − Load Capacitance − nF − Rise Time − ns 100 10 1000 0.01 1 10 100 CC = 6.5 V =

27 Low Side High Side 0.1 Figure 10 DRIVER-OUTPUT FALL TIME vs LOAD CAPACITANCE − Load Capacitance − nF 100 10 1000 0.01 1 10 100 CC = 6.5 V = 27 Low Side High Side − Fall Time − ns 0.1 Figure 11 SUPPLY CURRENT vs SUPPLY VOLTAGE CC − Supply Voltage − V 46 810 500 5000 14 3500 4000 4500 1000 1500 2500 12 CC I Supply Current −A 2000 3000 300 kHz 200 kHz 100 kHz 50 kHz 25 kHz 16 6000 5500 500 kHz = 25 = 50 pF Figure 12 SUPPLY CURRENT vs SUPPLY VOLTAGE CC − Supply Voltage − V 46 810 14 10 12 CC I Supply Current − mA 16 15 20 25 1 MHz = 25

= 50 pF 2 MHz
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 13 PEAK SOURCE CURRENT vs SUPPLY VOLTAGE Peak Source Current − A CC − Supply Voltage − V 46 810 0.5 14 2.5 3.5 1.5 12 Low Side High Side = 25 16 Figure 14 PEAK SINK CURRENT vs SUPPLY VOLTAGE Peak Sink Current − A CC − Supply Voltage − V 46 810 0.5 14 2.5 3.5 1.5 12 Low Side High Side = 25 16 1.0 1.2 1.4 1.6 1.8 2.0 4 6 8 10 12 14 16 Figure 15 INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE CC −

Supply Voltage − V IT − Input Threshold Voltage − V = 25 Figure 16 1.0 1.2 1.4 1.6 1.8 2.0 −50 −25 0 25 50 75 100 125 INPUT THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE − Junction Temperature IT − Input Threshold Voltage − V CC = 6.5 V
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 APPLICATION INFORMATION Figure 17 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A pulse-width-modulation (PWM) controller and a TPS2837 driver. The

converter operates over an input range from 4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3 A continuous load and the transient load is 5 A. The converter achieves an efficiency of 94% for V IN = 5 V, I load =1 A, and 93% for V IN = 5 V, I load = 3 A. C14 1 R9 90.9 k R8 121 k C9 0.22 CC RT FB COMP GND OUT DTC SCP U2 TL5001A C1 1 R10 1.0 k R2 1.6 k C2 0.033 C3 0.0022 C8 0.1 C4 0.022 R3 180 R4 2.32 k GND Q2 Si4410 R7 3.3 C6 1000 pF IN C5 100 C10 100 C11 0.47 3.3 V C13 10 C7 100 C12 100 Q1 Si4410 L1 27 U1 TPS2837 R1 1 k C15 1.0 R5 0 R11 4.7 RTN PGND LOWDR BOOTLO HIGHDR BOOT IN DT

CC R6 1 M Figure 17. 3.3 V 3 A Synchronous-Buck Converter Circuit
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 11 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 APPLICATION INFORMATION Great care should be taken when laying out the PC board. The power-processing section is the most critical and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source to the negative sides of C5, C10, and C11 should be as

short as possible. The negative terminals of C7 and C12 should also be connected to Q2 source. Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive traces. The bypass capacitor (C14) should be tied directly across V CC and PGND. The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very sensitive to noise pickup and should be isolated from the high-current power stage and be as

short as possible. The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply will be relatively free of noise.
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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 4040047/D 10/96 0.228 (5,80) 0.244 (6,20) 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 14 0.014 (0,35) 0.020 (0,51) 0.157

(4,00) 0.150 (3,81) 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) PINS ** 0.008 (0,20) NOM A MIN A MAX DIM Gage Plane 0.189 (4,80) (5,00) 0.197 (8,55) (8,75) 0.337 14 0.344 (9,80) 16 0.394 (10,00) 0.386 0.004 (0,10) 0.010 (0,25) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012
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PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page PACKAGING INFORMATION Orderable Device

Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS2836D ACTIVE SOIC 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2836 TPS2836DG4 ACTIVE SOIC 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2836 TPS2836DR ACTIVE SOIC 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2836 TPS2836DRG4 ACTIVE SOIC 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2836 TPS2837D ACTIVE SOIC 75 Green (RoHS & no Sb/Br) CU NIPDAU

Level-1-260C-UNLIM -40 to 125 2837 TPS2837DR ACTIVE SOIC 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 2837 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in

homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not

exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire

Device Marking for that device.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no

representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of

the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) (mm) Pin1 Quadrant TPS2836DR SOIC 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2837DR SOIC 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 1
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*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS2836DR SOIC 2500 340.5 338.1 20.6 TPS2837DR SOIC 2500 340.5 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 2
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