Seyi Ayorinde University of Virginia February 12 th 2015 Context BIST for FPGAs is now a mature study Many examples of different BIST methodologies and implementations BIST for FPGAs has been realized on commercial FPGAs primarily ID: 570583
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Slide1
Develop BIST for Custom-built FPGAs
Seyi
Ayorinde
University of Virginia
February 12
th
, 2015Slide2
Context
BIST for FPGAs is now a mature study
Many examples of different BIST methodologies and implementations
BIST for FPGAs has been realized on commercial FPGAs primarilyLeverage commercial FPGA configuration tools
2Slide3
Problem
Commercial FPGA configuration tools don’t work for custom-built FPGAs
Configuration format mismatch
Hardware mismatchResult - no available way to implement BIST on custom-built FPGAs
3Slide4
Proposed Solution
Extend open-source tools to be able to configure BIST structures to any arbitrary FPGA fabric, regardless of circuit design or FPGA architecture
4Slide5
Previous Work
Verilog-to-Routing tool (VTR) [1] – virtually maps
verilog
to FPGAsLimitation: No notion of hardware hand-wavy connections
5Slide6
Previous Work
DAGGER tool [2]– extension of old VTR (called VPR) with
bitstream
generationDesigned for a specific custom architecture (w/ specific architecture)Not available for use here at UVa (yet…)
Plenty of BIST implementations for FPGAs [3-7]
Discussions of results, but no provision of code
Used on commercial FPGAs
6Slide7
Approach
Design flexible custom-configuration tool-flow (currently working on that)
Develop/adopt TPG and ORA configurations for BLEs
First, search for verilog algorithms for implementing these thingsIf that fails, write my own
Configure and simulate TPG and ORA on individual BLEs (not full FPGA)
Test a BLE (as the CUT) with injected fault
7Slide8
Approach
Future work – configure to full FPGA structure and simulate
Future
future work – configure test structures to physical FPGA
8Slide9
Results
Algorithms for TPG and ORA structures written in
verilog
Initial condition statements for 1 or more BLE netlists to implement TPGs and ORAs.Verification of TPG & ORA functionality through simulation
9Slide10
Rough Milestone List
By 3/3
Find/write
verilog for BLE TPG and ORA
Finish configuration tool (generally) be able to configure any
verilog
file to any CLB structure
By 3/24
Simulated verification of BIST structures in CLBs
Tool-flow capability:
generation of single TPG and ORA for individual BLE
10Slide11
References
Jason
Luu
, Jerey Goeders, Michael Wainberg
, Andrew Somerville,
Thien
Yu,
Konstantin
Nasartschuk
,
Miad
Nasr, Sen Wang, Tim Liu,
Nooruddin
Ahmed, Kenneth B. Kent,
Jason Anderson
, Jonathan Rose, and Vaughn Betz. 2014. "VTR 7.0: Next Generation
Architecture and
CAD System for FPGAs." ACM Trans.
Recongurable
Technol. Syst. 7, 2, Article 6 (
July 2014
), 30 pages.
K
Siozios
et al
,
“DAGGER
: A Novel Generic Methodology for FPGA
Bitstream
Generation and its Software Tool Implementation”
Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS’05)
Stroud, C.; Konala, S.; Ping Chen; Abramovici, M., "Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)," VLSI Test Symposium, 1996., Proceedings of 14th , vol., no., pp.387,392, 28 Apr-1 May 1996Menon, P.R.; Weifeng Xu; Tessier, R., "Design-specific path delay testing in lookup-table-based FPGAs," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.25, no.5, pp.867,877, May 2006 Zhiquan Zhang; Zhiping Wen; Lei Chen; Tao Zhou; Fan Zhang, "BIST approach for testing configurable logic and memory resources in FPGAs," Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on , vol., no., pp.1767,1770, Nov. 30 2008-Dec. 3 2008 Rehman, S.-U.; Benabdenbi, M.; Anghel, L., "BIST for logic and local interconnect resources in a novel mesh of cluster FPGA," Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on , vol., no., pp.296,301, 2-4 Oct. 2013 Amouri, A.; Hepp, J.; Tahoori, M., "Self-heating thermal-aware testing of FPGAs," VLSI Test Symposium (VTS), 2014 IEEE 32nd , vol., no., pp.1,6, 13-17 April 2014
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