Gil Engel Senior Staff Design Engineer Analog Devices High Speed Converter Group January 29 2014 Introduction There is a rapid expansion of consumer demand for data services of all types Cable service providers ID: 152002
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Slide1
“What Will You Invent With The Latest Converter Innovations?”
Gil EngelSenior Staff Design EngineerAnalog Devices High Speed Converter Group
January 29, 2014Slide2
Introduction
There is a rapid expansion of consumer demand for data services of all types.Cable service providers Work to improve video quality from analog to digital to high definition.Include internet service at higher and higher data rates.Wireless service providersMove from analog to digital cellular to support more voice services.
Upgrading networks from 3G to LTE and beyond.Backhaul service providersMust upgrade systems to support increased traffic bandwidthMove to optical.
January 29, 2014
2Slide3
Introduction
There is a rapid expansion of consumer demand for data services of all types.Cable service providers Work to improve video quality from analog to digital to high definition.Include internet service at higher and higher data rates.Wireless service providers
Move from analog to digital cellular to support more voice services.Upgrading networks from 3G to LTE and beyond.Backhaul service providersMust upgrade systems to support increased traffic bandwidthMove to optical.Customers still expect data services at a nominal cost regardless of amount of data transferred!
January 29, 2014
3Slide4
Outline
Driving Applications for Mixed SignalNext Generation Converter CapabilitiesADC & DAC Innovations
New Architectural OpportunitiesConclusions
January 29, 2014
4Slide5
Outline
Driving Applications for Mixed Signal
January 29, 2014
5Slide6
ADC Timeline: Driving Application
January 29, 2014
6
1980
85
90
2010
05
00
95
Driving Applications
Mil/Aero
Instrumentation
Consumer Computer
Telecom Broadband
Networked MultimediaSlide7
The Driving Applications
January 29, 2014
7Slide8
Automotive Applications
January 29, 2014
8Slide9
Advanced TV: Analog Content Will Double in Three Years
January 29, 2014
9Slide10
Converters: Doorway Between Analog & Digital
January 29, 2014
10
Light
Sound
RF
Pressure
& Flow
Speed
Proximity
ADC
Digital Signal
Processing
Temp
Amp
DAC
Shared
Memory
…
SPI
I
2
C
I
2
C
SPI
SPI
Power Management
Amp
Digital Domain
Analog Domain
Control / MCU
Motion
Analog DomainSlide11
Converter Performance = Capacity
January 29, 2014
11
2nd
3rd
SNR
THD
SFDR
NSD
dB
Frequency (MHz)
BWSlide12
Outline
Driving Applications for Mixed SignalNext Generation Converter Capabilities
January 29, 2014
12Slide13
Applications (Speed vs. Accuracy)
January 29, 2014
13
Bits of
Resolution (also dynamic range, SNDR)
8
10
12
14
16
18
20
6
22
24
1,000
10,000
100,000
1,000,000
10M
100
Precision in Parts per Unit
100kHz
10kHz
1kHz
1GHz
100MHz
10MHz
1MHz
Speed / Bandwidth
10GHz
Process Control PLC/DCS
DVD Audio
CT
Ultrasound
Flat Panel
SONET
Distance/ Level
Industrial Automation
DVD Video
DVC
Cable TV
Defense/Aero
Comms
Bio Instruments
MRI
Precision Optics
Weigh Scale
Water Analysis
Digital X-Ray
Building Automation
Precision Measurement
Digital Camera
Auto Radar
Radar
Digital Oscilloscope
Monitor & Control
Spectrum Analyzer
DSL
Motor Control
High-Performance Frontier
Low-Performance
Patient
Monitoring
Wireless InfrastructureSlide14
Applications (Speed vs. Accuracy)
January 29, 2014
14
Bits of
Resolution (also dynamic range, SNDR)
8
10
12
14
16
18
20
6
22
24
1,000
10,000
100,000
1,000,000
10M
100
Precision in Parts per Unit
100kHz
10kHz
1kHz
1GHz
100MHz
10MHz
1MHz
Speed / Bandwidth
10GHz
Process Control PLC/DCS
DVD Audio
CT
Ultrasound
Flat Panel
SONET
Distance/ Level
Industrial Automation
DVD Video
DVC
Cable TV
Defense/Aero
Comms
Bio Instruments
MRI
Precision Optics
Weigh Scale
Water Analysis
Digital X-Ray
Building Automation
Precision Measurement
Digital Camera
Auto Radar
Radar
Digital Oscilloscope
Monitor & Control
Spectrum Analyzer
DSL
Motor Control
High-Performance Frontier
Low-Performance
Patient
Monitoring
Wireless Infrastructure
High Speed
PrecisionSlide15
Raw performance dimensions for HS ADCs/DACs
January 29, 2014
15
Trade-off
Trade-off
Trade-offSlide16
Performance Metrics – f70, FOM, BW, SNDR
SFDR – Spurious Free Dynamic Rangef70
– Frequency at which SFDR falls below 70dBc.FOM – Efficiency of conversion Simply put: higher score to the converter consuming lower power for a given SNDR and given bandwidth. R. Schreier’s figure of merit:
BW – Bandwidth synthesized or received.SNDR – Signal to Noise plus Distortion Ratio
January 29, 2014
16Slide17
Digital-to-Analog Converter Trends
January 29, 2014
17Slide18
Analog-to-Digital Converter Trends
January 29, 2014
18Slide19
Analog-to-Digital Converter
Trends
January 29, 2014
19
Precision
High SpeedSlide20
Performance Survey (ISSCC 1997-2007)
(courtesy of Dr. Boris
Murmann, Stanford)
January 29, 2014
20Slide21
Outline
Driving Applications for Mixed SignalNext Generation Converter CapabilitiesADC & DAC Innovations
January 29, 2014
21Slide22
DAC - Code Dependent Output Impedance
January 29, 2014
22
With digital input
x:
Ref. Lin
, et al.,
ISSCC
,
2009Slide23
DAC - Code Dependent Output Impedance(cont.)
January 29, 2014
23
It can be shown:
Biased on cascode minimizes “
Zon-Zoff
” improving HD3.
Ref. Lin
, et al.,
ISSCC
,
2009Slide24
DAC – Timing Error Dependent Distortion
January 29, 2014
24
Process mismatch will result in
clock-to-out mismatch (
σ
t
).
Every segment will have a different timing
error resulting in data dependent timing errors.
Ref. Doris,
et al.,
Proc.
ISCS
, 2003
Y. Tang, et al., JSSC, 2011Slide25
DAC – Timing Error Dependent Distortion(cont.)
January 29, 2014
25
Each segment has a
random timing error and may
also have a systematic error.
The timing error is integrated
among the bits toggling within
a period.
Sample
Period
Data-dependent
σ
t
timing error
Timing error limits performance for high
frequency applications.
Timing Error Compensation demonstrated recently.
Ref. Doris,
et al.,
Proc.
ISCS
, 2003
Y. Tang, et al., JSSC, 2011Slide26
DAC – Quad-switch current steering:
Minimizes data-dependent settling errors
January 29, 2014
26
By introducing a second pair of switches transitions occur even when data is not changing.
Ref. -
Schafferer
, ISSCC 2004
G. Engel, ISSCC 2012Slide27
LTE Carrier centered at 2.9GHz @3.2GSPS
January 29, 2014
27
>66dBc
ACLR >66dBc for 18MHz BW output at 2.9GHz
Ref. -
G. Engel, ISSCC 2012Slide28
Time-interleaved ADCs: the basic idea
January 29, 2014
28
Sample V
in
with M identical converters in a round-robin (cyclic) fashion
The sample rate of each converter is only
f
s
/M
Power and area grow linearly with MSlide29
Time-interleaved ADCs: the reality
January 29, 2014
29
M=4 in this exampleSlide30
Discrete versus Continuous Time
DS
January 29, 2014
30
Discrete time
DS
samples the input directly
Input structure same as Nyquist rate pipeline ADC, switched cap
Loop filter is discrete time, H(z)– switched cap poles and zeros
Continuous time
DS
samples after the loop filter
Input structure is passive
Loop filter is continuous time, LF(f)
“real” poles and zeros, generally need tuning
Either loop filter can be lowpass or bandpass
Pushes the switches “back”
Ref. H. Shibata,
et al.,
ISSCC
,
2012
G. Manganaro, “Advanced Data Converters”Slide31
Continuous Time
DS
January 29, 2014
31
Multiple possibilities of digitization
Low pass
Band pass
Quadrature, Complex…
Measured spectra from:
H.Shibata
,
“A DC-to-1GHz Tunable RF
ΔΣ
ADC Achieving DR = 74dB and BW = 150MHz at f0 =
450MHz Using
550mW”, ISSCC 2012
Low pass
Band pass
Ref. H. Shibata,
et al.,
ISSCC
,
2012Slide32
Outline
Driving Applications for Mixed SignalNext Generation Converter CapabilitiesADC & DAC Innovations
New Architectural Opportunities
January 29, 2014
32Slide33
Cell
Sites
Mobile BackhaulRadioControllerSitePre-Aggr.SiteAggr.Site
MetroNetwork
Aggr.
Site
Wireless Infrastructure Microwave Radio Links and Topologies
January 29, 2014
33Slide34
Transmit Architectures Low/High IF Sampling with Image Rejection
January 29, 2014
34
Familiar Heterodyne Architecture
Quadrature Balance Errors need to be managed
Offset and gain corrected in DAC
Phase corrected in DUC
Gain, Phase
& offset errorsSlide35
Move Converter Closer to Antennae
January 29, 2014
35
Familiar Heterodyne Architecture
Quadrature Balance Errors need to be managed
Offset and gain corrected in DAC
Phase corrected in DUC
Gain, Phase
& offset errorsSlide36
Transmit ArchitecturesDirect RF Synthesis
January 29, 2014
36
Potential for Direct to RF Synthesis
Eliminate Quadrature balance errors.
No gain or offset errors between converters.
No phase error
.Slide37
Multi-Band: 1800MHz + 2100MHz + 2600MHz
January 29, 2014
37
Fdac
= 2457.6MHz
4C WCDMA: PAR = 11.7dB, (no additional
backoff
)
FSC = 28mASlide38
Transmit ArchitecturesMulti-Band Direct RF Synthesis
January 29, 2014
38
Transmit multiple bands from a single converterSlide39
Heterodyne Receive Architectures
January 29, 2014
39
Conventional Heterodyne Receiver Architecture
Need frequency planning for
MxN
Mixer spurious
Different circuit & network optimization for different bandsSlide40
Move Converter Closer to Antennae
January 29, 2014
40
Conventional Heterodyne Receiver Architecture
Need frequency planning for
MxN
Mixer spurious
Different circuit & network optimization for different bandsSlide41
Receive ArchitecturesDirect RF Conversion
January 29, 2014
41
Potential
to Directly
to
Convert from Antennae
Single LPF for full band.
Tremendous dynamic range requirement.
As the converter moves, performance requirements increaseSlide42
The Dynamic Range Problem:Analog, Digital and the Converter
January 29, 2014
42
Signal processing is the extraction of the desired signal from the “noise.”
Moving to digital processing requires much better converter performanceSlide43
Conclusions
January 29, 2014
43
The CloudSlide44
Conclusions
Market shifts drive converter technologyNew converter technologies enable innovative technologyCommunication ArchitecturesDefense/Aerospace TechnologyIntegrated functionality
Next generation instrumentation and measurement equipment enables development of next generation convertersWHAT WILL YOU INVENT WITH THE LATEST CONVERTER INNOVATIONS!
January 29, 2014
44Slide45
References
Data-Over-Cable Service Interface Specifications, Downstream RF Interface Specification, Issue 12, CM-SP-DRFI-I12-111117, Cable Television Laboratories, inc., 17 November 2011.
“3GPP TS 45.005 Radio Transmission and Reception (Release 10)”, v10.4.0, March 2012.B. Razavi, “Principles of Data Conversion System Design”, IEEE Press, Piscataway, NJ, 1995.Rudy J. van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters 2nd ed.”, Kluwer, Dordrecht, The Netherlands, 2003.G. Manganaro, “Advanced Data Converters”, Cambridge University Press, 2011.A. Rodriguez-Vazquez, F. Medeiro, & E. Janssens, “CMOS Telecom Data Converters”, Kluwer Academic Publishers, 2003.C.-H. Lin, “A 12-bit 2.9 GS/s DAC with IM3< -60dBc Beyond 1GHz in 65nm CMOS”, IEEE JSSC, December 2009.S. Luschas
and H.-S. Lee, “Output Impedance Requirements for DACs”, IEEE International Symposium of Circuits and Systems”, vol. 1, 2003, pp. 861-864.G. Engel, “The Power Spectral Density of Phase Noise and Jitter: Theory, Data Analysis, and Experimental Results”, Analog Devices, AN-1067.P. Smith, “Little Known Characteristics of Phase Noise”, Analog Devices, AN-741.
K. Doris, “Mismatch-Based Timing Errors in Current Steering DACs”, IEEE Proceedings of ISCAS, 2003.
G. Engel, “A 14b 3/6GHz Current-Steering RF DAC in 0.18um CMOS with 66dB ACLR at 2.9GHz”, IEEE ISSCC, 2012
.
January 29, 2014
45Slide46
References
K. Poulton, “A 7.2-Gsa/s, 14-bit or 12-Gsa/s, 12-bit DAC in a 165-GHz ft
BiCMOS Process”, VLSI Symposium, 2011.Y. Tang, “A 14 bit 200MS/s DAC with SFDR >78dBc, IM3 <-83dBc and NSD <-163dBm/Hz across the whole Nyquist band enabled by dynamic mismatch mapping”, IEEE JSSC June 2011.H. Shibata, “A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW”, ISSCC 2012.
January 29, 2014
46Slide47
January 29, 2014
47