NoC Router Estimation Andrew B Kahng Bill Lin and Siddhartha Nath UCSD CSE and ECE Departments abk billlin sinath engucsdedu Outline Motivation ID: 478910
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Slide1
Explicit Modeling of Control and Data for Improved NoC Router Estimation
Andrew B.
Kahng
+*
, Bill Lin
*
and Siddhartha
Nath
+
UCSD
CSE
+
and ECE
*
Departments
{
abk
,
billlin
,
sinath
}@
eng.ucsd.eduSlide2
Outline
Motivation
Our work: Overview
Methodology
Flit-level power estimationSummary
2Slide3
NoC Modeling So Far… (ORION)
3
Arbiter
XBAR
BUF I
BUFE
BUFW
BUFN
BUFS
Link
Link
Link
Link
SRC
Link
Link
Link
Link
SINK
ORION1.0
(2002)
6NOR + 2INV + DFF
ORION2.0 (2009)
6NOR + 2INV + DFF
Leakage power
Clock powerSlide4
What Is The Problem?
RTL code mismatch
Logic transformation and technology mapping mismatch4
Arbiter
XBAR
BUF I
BUFE
BUFW
BUFN
BUFS
Link
Link
Link
Link
SRC
Link
Link
Link
Link
SINK
6NOR + 2INV + DFFSlide5
How Bad Is It?
Router RTL generators:
Netmaker – Cambridge, UKStanford NoC - Stanford
460%
89%
Why such large errors?
Assumed logic template inaccurate
Control logic not modeled
Implementation details missing
5Slide6
Motivation
Our work: Overview
Methodology
Flit-level power estimation
Summary Outline
6Slide7
P - #Ports
V - #VCs
B - #BUFs
F – Flit-width
Key idea: No assumed logic template
Component models derived from actual RTL synthesized with cell libraries
We Propose: Step 1
Derive router component block parametric models
from
post-synthesis netlists
P
V
B
F
#
Instances102832
330082832
211252832825
~P
2
~P
2
PV
BF
# Instances
52
816
4005
2832
825
528641673
~F
XBAR ~ P
2F7Slide8
We Propose: Step 2
Automatic fitting of models with
post-P&R power and area8
XBAR ~ P
2
F
P
V
B
F
Area
5
28161439.9
528322916.0
528645867.4
828327465.1
LSQR
XBAR
area = a1.
P2F + a0
Key idea: Capture implementation
details using automatic regression fit
Characterization
performed only once and usable for multiple design space explorationsSlide9
Motivation
Our work: Overview
Methodology
Flit-level power estimation
Summary Outline
9Slide10
Model Development
Two RTL generators:
Netmaker (Cambridge, UK)Stanford NoCSP&R tools:
Cadence RC & Synopsys DC for hierarchical synthesis to analyze each blockCadence SOC Encounter for P&R
NoC
router RTL generators
Impl
params
: Clock Frequency
µArch
params
: P, V, B, F
Synthesis and P&R: DC/RC, SOCE
Analysis of blocks: XBAR, SW & VC arbiter, Input & Output buffers
New models for each component block
Component
ModelXBARP
2FSWVC9(P2V2 + P2 + PV – P)InBUF
180PV + 2PVBF + 2P2VB + 3PVB + 5P2B + P2 + PF + 15POutBUF25P + 80PV
CLKCTRL0.02(SWVC + InBUF + OutBUF)
10Slide11
Overall Methodology
Manual
Quick and easyMisses implementation details
Basic
Regression fit
Manual
Estimates for gate count
ORION_NEW models
LSQR
Technology
Library
Cell area
Cell leakage
Pin cap.
Internal
e
nergy
Area
Power: leakage, internal, switching
Post P&R
data per block
Std. cell count
& area
Leakage power
Internal power
Switching power
LSQR
Accurate (captures
implementation details)
One-
tim
e overhead
(generation
of
P&R
training data points)
11Slide12
POWER
6.5x
reduction
Results: Area And Power
12
AREA
4x
reduction
Methodology scales across technologies, router RTL generatorsSlide13
Motivation
Our work: Overview
Methodology
Flit-level power estimation
Summary Outline
13Slide14
Flit-level Power Estimation
Dynamic power estimation using flit-level bit encodings
Have integrated with full-system NoC simulator (GARNET)
Post-P&R router netlist
Testbench
Gate-level simulation
VCD
Power analysis
Power Report
Regression fit
ORION_NEW models
Flit-level power model
GARNET
gem5
Flit-level power estimates
14Slide15
Results: Flit-level Power
Accurate estimation of flit-level dynamic power
15
3.6x
reductionSlide16
Motivation
Our work: Overview
Methodology
Flit-level power estimation
Summary Outline
16Slide17
Summary
New hybrid modeling methodology:
relax the template mindsetExplicitly models control and data signalsCaptures RTL and implementation details
Using proposed parametric regression methodology, worst-case estimation errors reduced by a factor of
6.5x from ORION2.0 for power4x from ORION2.0 for areaWe propose an application of our methodology for flit-level dynamic power modeling and integration with GARNET3.6x worst-case error reduction in dynamic power estimation
Ongoing: Non-parametric modeling of post-P&R power and area
17Slide18
Thank You !
18Slide19
Back
up
19Slide20
Regression analysis approach
Multi-step regression fit
Step 1: Fit instances of each router component with post-layout instance counts
a1
. Instsmodel <component> + a0 = Inststool
<component>
Step 2a: Fit area of each router component with post-layout area
b
1
.
Insts
R
model <component> + b
0 = Areatool <component>InstsR
model <component> = a1. Instsmodel <component> + a0
Step 2b: Fit power of each router component with post-layout power (leakage, internal, switching separately)
{c
5, d5, e5}. InstsR
model XBAR + {c4, d4, e4}.InstsR model SWVC + {c
3, d3, e3}.InstsRmodel InBUF + {c2, d2, e
2}.InstsRmodel OutBUF + {c1, d1, e1}.InstsR
model CLKCTRL + {c0, d0, e0} = {Pleak tool
,Pint tool, PSW tool}
20Slide21
Related work
Architecture templates
ORION2.0Gate-level analytical modelsParametric regressionPre- and post-layout power estimationRTL simulations
Non-parametric regressionMARS
NoC
Modeling
Regression model
Parametric
Non-parametric
ORION_NEW + regression; flit-level
Circuit model
Arch templates
Analytical
Significant
Departure:
Relax
the “template” mindset
Control
Tool
21Slide22
Results
Avg. estimation error in
# instances
reduced from
109.5%
to
8.8%
Avg. estimation error in
area
reduced to
9.8%
Avg
estimation error in
power reduced to 4.58%22