Design Shah Zafrani CS 6021 Fall 17 Cryptography Basics There are two main types of commonly Cryptographic Algorithms Symmetric Key AES is the most commonly used form of this because of its speed ID: 674366
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Slide1
Survey of Crypto CoProcessor Design
Shah Zafrani
CS 6021 – Fall ’17Slide2
Cryptography Basics
There are two main types of commonly Cryptographic Algorithms :
Symmetric Key
AES is the most commonly used form of this because of it’s speed
Better for encrypting messages
Asymmetric Key
RSA is used because of it’s ability to securely exchange keys
Used for key exchange primarily
Not ideal for message encryption because it’s computationally heavySlide3
Hash Algorithms are crucial too!
Hashing algorithms are used to authenticate data.
MD5 Checksums, SHA-1, and SHA-256 are just a few.
Some Crypto
CoProcessors
also speed up these algorithmsSlide4
FPGA vs ASIC
ASIC (Application Specific Integrated Chip)
More Power Efficient
Takes longer to design
Relatively difficult to modify
FPGA (Field Programmable Gate Array)
Short design cycle enables quick time-to-market
Low cost
Easy to update and modifySlide5
FPGA based CoProcessor
This is an implementation that is coupled with a MIPS Processor but can be extended to others
All instructions fetched by the main processor that are not designed for it are sent to the FPGA.
CoProcessor
is Parameterized so that only as many rounds as needed are processed
Designed specifically for AESSlide6
AES implementation
Completes rounds
iteratively
Slide7
Pipelined AES Implementation
Takes advantage of parallelization to allow multiple rounds to run concurrentlySlide8
MIPS DatapathSlide9
MIPS with AES CoProcessorSlide10
AFPC Implementation
A
pplication
F
lexible
co
P
rocessor
for
C
rypto
CMOS 0.18um fabrication
Uses VLIW (Very Long Instruction Word) 160 bits wide
32 bits for op code, and 128/4 bits for up to four functional units
Allows for AES, DES, MD5, SHA, and othersSlide11
Overview of AFPCSlide12
Functional Unit DetailsSlide13
SRCP Implementation
ASIC CMOS produced solution
Resistant to Side Channel Attacks
Simple Power Analysis
Differential Power Analysis
Electromagnetic Analysis
Supports AES, DES, IDEA, RC6
Reconfigurable using PE ArraysSlide14
SRCP OverviewSlide15
Scan Channel Analysis VisualizedSlide16
References (APA Style)
Parameterized AES-Based Crypto Processor for FPGAs. (2014). 2014 17th
Euromicro
Conference on Digital System Design, Digital System Design (DSD), 2014 17th
Euromicro
Conference on, Digital System Design (DSD), 2013
Euromicro
Conference on, 465.
doi:10.1109/DSD.2014.90
Yang
, X., Yu, X., Dai, Z., & Zhang, Y. (2008). Accelerated flexible co-processor architecture for crypto information. *2008 4Th IEEE International Conference On Circuits And Systems For Communications, ICCSC*, (2008 4th IEEE International Conference on Circuits and Systems for Communications, ICCSC), 628-632.
doi:10.1109/ICCSC.2008.139
Shan, W., Fu, X., &
Xu
, Z. (2015). A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA.
IEEE Transactions On Computer-Aided Design Of Integrated Circuits & Systems
,
34
(7), 1201-1205.