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IRDS  Emerging Research Devices and Architectures NanoCrossbar Workshop IRDS  Emerging Research Devices and Architectures NanoCrossbar Workshop

IRDS Emerging Research Devices and Architectures NanoCrossbar Workshop - PowerPoint Presentation

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Uploaded On 2018-10-31

IRDS Emerging Research Devices and Architectures NanoCrossbar Workshop - PPT Presentation

  Paul Franzon North Carolina State University Raleigh NC paulfncsuedu 9195157351 httpwwwecencsueduerlfacultypaulfhtml Thanks Thanks to Rambus for hosting this event Spherically Gary Edge VP for Research and Jaimie Stuart for Logistics ID: 705765

research device devices computing device research computing devices cmoscmosnon achieving emerging learning crossbarsfor state ncsu probabilistic flash nvm scm

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Slide1

IRDS Emerging Research Devices and Architectures NanoCrossbar Workshop 

Paul FranzonNorth Carolina State UniversityRaleigh, NCpaulf@ncsu.edu919.515.7351http://www.ece.ncsu.edu/erl/faculty/paulf.htmlSlide2

ThanksThanks to Rambus for hosting this eventSpherically Gary Edge, VP for Research and Jaimie Stuart for LogisticsSlide3

BackgroundInternational Roadmap for Semiconductors (ITRS) used to sponsored by SIANow International Roadmap for Devices and Systems (IRDS) sponsored by IEEE

Emerging Research Devices (ERD) Chapter had a subsection called Emerging Research Architectures (ERA). BothEdited chapter in odd yearsHelp workshops in even yearsHeld a workshop on Storage Class Memory in 2012Been wanting to do workshops in other areas but lacked good definitionFor 2016 two workshopsNanocrossbarApproximate/ Stochastic/ Probabilistic computingSlide4

Core Group - ERAPaul Franzon, NCSU (editor)An Chen, IBM (ERA chair)Shamik

Das, MitreMatthew Marinella, SandiaErik DeBenidictis, SandiaGeoff Burr , IBMSlide5

Program-Centric

(performance and components dictated by designer)

Data-Centric

(performance and/or

components influenced

by

the data that is passed through the system

)

Good old-fashioned

Von NeumannNon-Von Neumann MemoryProcessorNon-VN Processor(including less-than-reliable VN)Trained off-lineTrained in-lineCMOSNon-CMOSCMOSNon-CMOSCMOSNon-CMOSCMOSNon-CMOSCMOSNon-CMOS

Deterministic/reliable

Non-

deterministic

SRAM

DRAM

Flash

NVM crossbarsfor S-SCM,M-SCM

Logic-in-memory

FPGA

NVM-basedFPGA

Coupledoscillators

True North

Execution of pre-trained ANN

OhmicWeave

SupervisedANN learning

CMOS

“Nextswitch”

New learning algorithms(unsupervised, reinforcement)

HTM

Probabilisticcomputing

Approximatecomputing

CMOSbeyond the designenvelope

Crossbarsfor STDP

Crossbarsfor backprop

GPUs

Coarse-GrainedReconfigurableArchitectures

Probabilistic Learning

RBM

Bayesian

TCAM

Analogcomputing

Analogcomputing(w/ Flash)

Quantumcomputing

Accelerators(multimedia, etc.)

NV computing

MLAcceler-ators(Convolution,SVM, ML)

AutomataProcessing

Active

InterconnectSlide6

2015 ChapterStarted tracking NanoCrossbars explicitlySlide7

Goals of WorkshopIdentify and quantify the state of the art in devices, design, modeling, fabrication, and employment of Nano-enabled Crossbars for computing.

Identify the research barriers impeding the use of NanoCrossbars for computing.Slide8

Questions asked to presentersGeneral, including memoriesWhat is the status of achieving linear repeatable response, low power, sufficiently long retention, fast writes, sufficiently distinguishable resistances in different states, and long write endurance in one nanoscale device?

Is the access device issue solved? What are the remaining issues?Slide9

… QuestionsNeuromorphic computingWhat are the requirements on device linearity, scalability and dynamic range?

What is achieved today?What are the tradeoffs exposed in achieving this?What style of non-traditional computing is best suited to nanodevice arrays? E.g. spiking neuron, deep network, full logic map, etc.Why?What are the specific gaps in device properties that are preventing us from achieving this paradigm?Slide10

… QuestionsAnalog computingWhat are the requirements on device linearity, scalability and dynamic range?

What is achieved today?What are the tradeoffs exposed in achieving this?What is the required device yield? What mechanisms are available for implementing working arrays in the presence of <100% yield?What levels of noise during readout can be tolerated?To what degree could closed-loop control (e.g., iterative resistance-tuning for higher accuracy) be available during device write?Slide11

Agenda0900– 0930 : Introduction: Paul Franzon, NC State University0930 – 1020 : Matt Marinella, Sandia

1020 – 1040 : Break1040 : 1120 : Geoff Burr IBM1120 – 1200 : Catchup1200 – 1300 : Lunch1340 : Dmitri Strukov, UCSB1420 : Kevin Cao, ASU 1420– 1440 : Break 1440 - 1520: Miao Hu, HPE

520

– 1600 : Wei Lu, UMich

1600

1640

:

Gert Cauwenberghs, UCSD (via webex)