Mitigating Wordline Crosstalk using Adaptive Trees of Counters - PowerPoint Presentation

Slide1

Mitigating Wordline Crosstalk using Adaptive Trees of Counters

Mohammad Seyedzadeh

, Alex Jones, Rami MelhemUniversity of Pittsburgh

Slide2

2

DRCAT: Dynamically Reconfigured

Counter based

Adaptive Tree

Deep-scaled

D

RAM

C

ells

DRAM

C

ells

Wordline

Crosstalk

in

DRAM

DRAM S

caling

 

✔

H

igh Memory Capacity

✖

Voltage

Fluctuations

Slide3

2

DRCAT: Dynamically Reconfigured

Counter based

Adaptive Tree

Deep-scaled

D

RAM

C

ells

DRAM

C

ells

The malicious exploit of

this crosstalk

by

repeatedly

accessing a row to induce this effect is known as

row hammering

.

Wordline

Crosstalk

in

DRAM

Row of Cells

DRAM

Bank

Row of Cells

Wordline

Victim Row

Aggressor Row

Victim

Row

Slide4

Wordline

Crosstalk in DRAM

Probabilistic and Deterministic Solutions

CAT

: Counter based Adaptive

Tree

Evaluation

Conclusion

Outline

3

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Slide5

4

DRCAT: Dynamically Reconfigured

Counter based

Adaptive Tree

Deep-scaled

D

RAM

C

ells

Deterministic Approach

Probabilistic

Approach

Wordline

Crosstalk in

DRAM: Related Work

Static Counter Assignment

(SCA)

Probabilistic

Row Activation (PRA)

Slide6

Probabilistic

Row Activation (PRA)

5

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Probabilistic

Approach

Deep-scaled

D

RAM

Cells

RNG(p)

Using a Random Number Generator to refresh the victim rows with the probability of ‘p’.

Slide7

Probabilistic

Row Activation (PRA)

6

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Refresh threshold:

#

of

aggressor row

accesses before read disturbance errors occur in victim rows.

LFSR-based

RNG

Pseudo Random Number Generator (PRNG)

PRA Failure Probability for 5 years

Slide8

Static Counter Assignment

(SCA)

7

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Power to maintaining

Counters

Precise

Refresh

Power

Power to maintaining

Counters

Conservative

R

efresh

P

ower

Deep-scaled

D

RAM

C

ells

C

0

C

m

.

.

.

C

N-1

.

.

.

.

.

.

.

.

.

Deep-scaled

D

RAM

C

ells

C

0

C

n

Slide9

Static Counter Assignment

(SCA)

8

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Non-uniform row access patterns in DRAM banks because of data locality

Unutilized Counters

Slide10

How to Efficiently

Leverage

Counters in the Crosstalk Mitigation?

8

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Slide11

9

DRCAT: Dynamically Reconfigured

Counter based

Adaptive Tree

Our Solution:

Counter-based Adaptive Tree (CAT)

Expired Counter

DRAM BANK (N rows)

Active Counter

Row Address

Slide12

10

DRCAT: Dynamically Reconfigured

Counter based

Adaptive Tree

Our Solution:

Counter-based Adaptive Tree (CAT)

Expired Counter

Active Counter

DRAM BANK (N rows)

Row Address

Slide13

CAT: Counter

based Adaptive Tree

11

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

PRCAT: Periodically

Reset

CAT

Burst Refresh Mechanism

Reset CAT at the end of each refresh Interval

DRCAT: Dynamically Reconfigured CAT

Distributed Refresh Mechanism

Reconfigure CAT during consecutive refresh intervals

Slide14

PRCAT: Periodically

Reset CAT

12

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

C0

Burst Refresh

64ms

64ms

Slide15

PRCAT: Periodically Reset CAT

12

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Burst Refresh

64ms

64ms

I0

C

0

C1

C0

Slide16

C1

PRCAT: Periodically Reset CAT

12

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

I0

C

0

I3

I2

C1

I4

C3

C6

I5

C4

C2

C5

I1

Burst Refresh

64ms

64ms

Slide17

PRCAT: Periodically Reset CAT

12

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

I0

C

0

I1

I3

I2

C1

I4

C3

I5

C4

C2

C5

I6

C7

C6

Burst Refresh

64ms

64ms

Reset CAT

C6

C

0

Build CAT from the Root

Slide18

DRCAT: Dynamically Reconfigured CAT

13

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

I0

C

0

I1

I3

I2

C1

I4

C3

I6

C7

C6

I5

C4

C2

C5

C6

C2

C5

Distributed Refresh

64ms

64ms

Slide19

13

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

I0

C

0

I1

I3

I2

C1

I4

C3

I6

C7

I5

C4

C2

64ms

64ms

DRCAT: Dynamically Reconfigured

CAT

C5

C2

I5

C6

Distributed Refresh

During each row access, the tree structure is traversed sequentially by chasing the pointers to find the counter assigned to a specific row address.

Slide20

14

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Synopsys Design Compiler

PARSEC, SPEC

, Commercial and

Biobench

Power Overhead

Performance Overhead

Kernel Malicious Attack

USIMM

Simulator:

Two

3.2GHz cores, 2 channels(each 8GB DIMM), 1 rank/channel 8 banks/rank, 64K rows/

bank

Experimental Settings

Slide21

Power Overhead

15

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Power overhead for DRCAT

in dual-core systems is 4.5%, which is an improvement over the 12% and

13%

incurred in

PRA

and SCA.

Slide22

Performance Overhead

16

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

DRCAT, PRCAT and PRA incur very low performance overhead (<0.5%).

Slide23

Sensitivity

Analysis

17

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

DRCAT

reduces the

power overhead in

quad-core systems to 7%, which is an improvement over the 21% and 18% incurred in SCA and

PRA.

Refresh Thresholds

Mapping Policy

& Number of Cores

Scaling down DRAM technology exacerbates the crosstalk problem leading to a decrease in the refresh threshold.

Slide24

Performance Overhead under

Malicious attacks

18

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

As

expected, more intensive attacks leads to higher ETO since it causes more refreshes.

<0.9%

Slide25

Conclusion

19

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Proposed a

non-uniform counter assignment,

Counter-Based Adaptive Tree

,

to more precisely determine the aggressor rows.

Introduced a scheme, DRCAT, for

dynamically reconfiguring the CAT to track the temporal changes in memory access patterns .

Demonstrated that

a small number of counters can be implemented on chip to mitigate wordline

crosstalk.DRCAT

avoids wordline crosstalk during normal execution and protects against malicious attacks.

Slide26

20

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Thank you for your attention!

Question?

Slide27

Backup Slides

Slide28

Hardware

Overhead

21

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Hardware energy (per bank) and area of DRCAT, PRCAT and SCA for different number of

counters

The specification of the PRNG used for PRA. The reported energy for PRNG (

eng_PRNG) is for generating 9-bits per row access.

M

Energy: dynamic (

nJ

per row access) and

static (nJ per refresh interval)

Area

(mm

2

)

PRNG

DRCAT

PRCAT

SCA

DRCAT

PRCAT

SCA

dynamic

static

dynamic

static

dynamic

static

32

3.05E-04

5.77E+03

2.91E-04

5.55E+03

1.41E-04

3.16E+03

3.16E-02

3.04E-02

1.86E-02

Area

4.0E-3

64

4.30E-04

1.39E+04

4.09-04

1.32E+04

1.92E-04

8.81E+03

6.12E-02

5.86E-02

4.04E-02

Throughput(

Gbps

)

2.4

128

5.83E-04

2.77E+04

5.50E-04

2.63E+04

2.22E-04

1.44E+04

1.16E-01

1.11E-01

6.04E-02

Power(

mW

)

7

256

8.72E-04

5.44E+04

8.25E-04

5.13E+04

3.12E-04

2.39E+04

2.23E-01

2.11E-01

1.00E-01

Eff.(

nj

/b)

2.9E-3

512

1.17E-03

1.06E+05

1.10E-03

1.02E+05

4.25E-04

4.52E+04

3.93E-01

3.75E-01

1.72E-01

Eng_PRNG

(

nj

)

2.62E-2

Slide29

Static Counter Assignment (SCA)

22

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Slide30

Sensitivity

to

the Maximum CAT depth23

DRCAT: Dynamically

Reconfigured

Counter based

Adaptive Tree

Crosstalk mitigation power overhead per bank for DRCAT using from 32 to 512 counters and different maximum CAT levels (6 to 14).