the pendingnarrow GND traces Improve connection of IC GND to GND plane add vias around the GND pin or under the IC The gate drive signal path is way long and crosses the sense resistor Flip the FET 90deg CW and route the gate drive on the bottom also move R5 and R4 closer to IC Th ID: 635176
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Slide1
Avoid the small antennas
(the pending/narrow GND traces)
Improve connection of IC GND to GND plane (add
vias
around the GND pin or under the IC)Slide2
The gate drive signal path is way long and crosses the sense resistor. Flip the FET 90deg CW and route the gate drive on the bottom (also move R5 and R4 closer to IC). This won’t create problem because will be short path (also widen a bit the trace to reduce the parasitic L).Slide3
Rotate U3 90degs CW and U10 90degs CCW. In this way you will have better (and wider) lanes for VIN, VOUT,
GNDin and
GNDout…
Tend to fill the empty space with copper (better thermal), keeping a good separation
(25 mils are enough)
between the various lands.Slide4
Add more
vias
to improve the connection between GND plane and GND lands. 20-30mils diameter vias can manage up to 1Amp each, 0.5Amp thermal (remembering by heart, should doublecheck)Slide5
Because of having only 2 layers
pcb
, I’m very sceptic on separate GNDs: this can force high current to flow into the wrong/unexpected path.I’m more for a single full GND plane (with some little exceptions)Slide6
The VIN trace is not nice…
Keep VIN from the diode running externally on top up to this
vias.Then you go on bottom to reach R15