IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.30,NO.2,FEBRUARY1995 - PDF document

IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.30,NO.2,FEBRUARY1995 (a)(b)Fig.2.MOSdevicestructures,(a)regular,(b)ring-shaped. (a) Fig.3.Ring-shapedNMOSdevicecharacteristics,(a)from0to3Vin0.5Vsteps),(b)from1Vto3Vin1Vsteps).Figs.3and4depictthemeasuredIVcharacteristicsofring-shapedNMOSandPMOSdeviceswithdrawndimensions m 0.1 m.Wenotethat mV, mV,andtheNMOSandPMOSsubthresholdslopesare85mV/decand90mV/dec,respectively.Whilethedevicesandcircuitshavebeensuccessfullycharacterizedforsupplyvoltagesashighas3V,long-termreliabilityissuessuchashotelectroneffectsandgatetunnelingcurrentstypicallylimittheoperatingvoltagetoapproximately2V. (a) Fig.4.Ring-shapedPMOSdevicecharacteristics,(a)3Vin0.5Vsteps),(b)1Vto3Vin1Vsteps).Sincethering-shapedgeometryofFig.2(b)suffersfromalargesourcejunctioncapacitance,itprovesbenecialifonlythedrainterminalappearsinthecriticalsignalpath.Thus,circuittopologiessuchaspasstransistorsorstackeddevicescannotbeusedefciently.Thisobservationcanbesummarizedasadesignconstraintforcircuitsusingring-shapedstructures:nopathfromhigh-speednodestothesupplyrailsmayincludeseriesdevices.Inaddition,itisdesirabletoavoidthegate-channelcapacitanceofPMOStransistorsinthecriticalpathbecausethetrade-offbetweentheirtransconduc-tanceandinputcapacitancelimitsthemaximumachievableTheprincipalchallengeindesigningthecircuitsdescribedherehasbeentodeveloptopologiesthatperformtherequiredfunctionswhilecomplyingwiththeaboveconstraints.III.FA.ArchitectureThe1/2frequencydivideremploystwo -latchesinamaster-slavecongurationwithnegativefeedback.Inhigh- RAZAVIetal.:DESIGNOFHIGH-SPEED,LOW-POWERFREQUENCYDIVIDERS (a) Fig.5.Master-slavedividerswith,(a)singleclock,(b)complementaryspeedmaster-slavedividers,itiscommonpracticetodesigntheslaveastheªdualºofthemaster[Fig.5(a)]sothattheycanbebothdrivenbyasingleclock[5].However,dualityrequiresoneofthelatchestoincorporatePMOSdevicesinthesignalpath,henceloweringthemaximumspeed.Toavoidthisdifculty,asshowninFig.5(b),thedividerutilizestwoidentical -latchesthataredrivenbycomplementary and .Inordertominimizetheskewbetween and ,thenoninvertedphaseisdelayedbymeansofacomplementarypassgatehavingdevicesidenticalwiththoseinthemaster.Althoughtheskewincreasesastheinputtransitiontimebecomescomparablewiththeperiod,simulationsindicatethatitislessthan10psfora13GHzsinusoidalinput.NotethatthepassgateusedhereisnotinthedividerloopandhencedoesnotviolatetheconstraintdescribedinSectionII.Thecapacitanceseenattheinputofthisgatesimplycontributeslatencytothecircuit.B.CircuitDetailsFig.6depictsthedividercircuit.Eachlatchconsistsoftwosensedevices( and inthemasterand and theslave),aregenerativeloop( and inthemasterand and intheslave),andtwopull-updevices( and inthemasterand and intheslave).When ishigh, and areoffandthemasterisinthesensemode,while and areonandtheslaveisinthestoremode.When goeslow,thereverseoccurs.Notethatthecircuitusesnostackedorpasstransistors.Also,thegate-channelcapacitanceofthePMOStransistorshardlyaffectsthecriticalpathbecausethesedevicesare(velocity)saturatedalmostfortheentirevoltageswingatnodes ,and .(Atmaximumspeed,theseswingsarenotrail-to-rail.)Incontrastwithconventionallatchtopologies,the circuitusedinthisdividerdoesdisableitsinputdeviceswhenitgoesfromthesensemodetothestoremode.Whilethiswouldposetimingproblemsinageneraldigitalcircuit, Fig.6.Dividercircuit. Fig.7.Dividersimulatedwaveforms.itdoesnotpreventthedividerfromfunctioningproperly.Toexplainthereason,wemaketwoobservations.First,sincetheinputdevicesofeachlatchare -type,theycanchangethestateonlyifoneoftheinputsgoesfromlowtohigh(andtheotherfromhightolow).Second,wheneachlatchisinthesensemode,neitherofitsoutputscangofromlowtohighbecausethePMOSpull-updevicesareoff.Thus,if,forexample,themasterisinthesensemodeandtheslaveinthestoremode,themaster'soutputscanonlygofromhightolowandhencecannotoverridethestatestoredintheslave.ShowninFig.7arethedivider'ssimulatedwaveformsat1GHzclockfrequency.WhenthePMOSdevicesareon,they IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.30,NO.2,FEBRUARY1995 Fig.8.Simulatedspeedofthreedividertopologiesversussupplyvoltage. Fig.9.Dividerdiephotograph.slightlydegradethelogiclowlevelandalsoprovideacurrentpathfrom toground,therebydissipatingstaticpower.Notethatinthesensemode,bothoutputsofeachlatcharelow,onebeingpulledlowbyaninputdeviceandtheothermaintainingalowstatefromthepreviouscycle.UsingsimulationsbasedonourCMOSdevicemodels,wehavecomparedtheperformanceoftheproposeddividertopologywiththatoftwohigh-speeddividersreportedin[5]and[6].PlottedinFig.8isthemaximumclockfrequencyofeachcircuit, ,asafunctionofsupplyvoltage,indicatingatleastafactoroftwoimprovementinspeed.Thehigherspeedoftheproposeddividerisduetothestrongpositivefeedbackineachlatchaswellasfewerstagesinthecriticalsignalpath.Notethatifregular,ratherthanring-shaped,devicesareusedhere,thespeeddecreasesbyapproximately20%. (a) Fig.10.Measureddividerinput/outputwaveformsfor(a)=10C.ExperimentalResultsThedividerhasbeenfabricatedinour0.1 mCMOStechnology.Fig.9showsaphotographofthedie,whoseactiveareameasuresapproximately50 m m.Forinputtermination,three -wellresistorsareusedinparallelsothattheycanbedisconnectedonebyonetoprovideanapproximatevalueof50 .Thecircuithasbeentestedonwafer(atroomtemperature)usingahigh-speedPicoprobetoapplytheinputandaCascademulticontactprobetomeasuretheoutputaswellasprovidepowerandgroundconnections.Noattempthasbeenmadetogeneratelargeoutputswingsoffthechipasthesetupprovidessufcientlyhighsignal-to-noiseratio,allowingdirectmeasurementofamplitudesinthemillivoltrange.Theoutputstageofthecircuitissimplya3 m 0.1 mNMOStransistordrivinga50 ShowninFig.10(a),(b),and(c)arethemeasuredinputandoutputwaveformsofthedividerat 5,10,and13.4GHz, RAZAVIetal.:DESIGNOFHIGH-SPEED,LOW-POWERFREQUENCYDIVIDERS Fig.10.=13GHz(inputamplitudenottoscale). Fig.11.Measureddividerspeedversussupplyvoltage. Fig.12.Dividerpower-speedtrade-off.respectively.Inthismeasurement,thesupplyvoltageis2.6Vandtheinputamplitudeisrail-to-rail.For 13.4GHz,thecircuitbeginstomisspulsesanddividesbythree.Inordertoassessthelow-voltageperformanceofthecircuit,thesupplyvoltagewasvariedfrom1.2to2.6V,yieldingthe variationdepictedinFig.11.Thedividerexhibitsan of5GHzat 1.2Vand10GHzat 2V.Asacomparison,the0.1 mSOIimplementationin[5]achievesan of2.6GHzat 2V.TheslightdifferencebetweensimulatedandmeasuredresultsofFigs.8and11isattributedtoinaccuraciesinthedevicemodelsusedinsimulations. Fig.13.Phase-lockedlooparchitecture. Fig.14.Current-controlledoscillator.Themeasuredspeed-powertrade-offoftheprototype(in-cludingI/Obuffers)isshowninFig.12.Thecircuitdissipates2.6mWat5GHz(with V)and28mWat13.6GHz(with Sincetheprimarygoalofthisdesignhasbeentoachieveahighspeed,allthedevicesarering-shapedandhencehaveaminimumwidthof8.8 m.Forclockfrequenciesbelow10GHz,adesignemployingsmallerdevicescanfurtherreducethepower.IV.PA.ArchitectureThePLLarchitectureisshowninFig.13.Itconsistsofaninputbufferandaloopcomprisingamixer,alow-passlter(LPF),acurrentamplier,andacurrent-controlledoscillator(CCO).Theoscillatoroutputdrivesanopen-drainNMOSdevice,deliveringafewmilliamperesofcurrenttoanexternal TheinputbufferisdesignedsoastopresentthesamewaveformandimpedancetothemixerasdoestheVCO.Thisreducesthestaticphaseerrorbecauseathighspeeds,theoutputofmixersbecomessensitivetoboththewaveformandthedrivingimpedanceseenattheirinputs.WhileitisdesirabletoimplementthePLLindifferentialformsoastosuppresstheeffectofcommon-modenoise,lowsupplyvoltages( 3V)limittheheadroom,makingitdifculttoutilizedifferentialcontrolforCMOSoscillators.Thus,thePLLcircuitissingle-ended,butitemployscurrent-modecontrolsignalstolowerthesensitivitytosupplyandsubstratenoise.B.CircuitDetailsFig.14showsthecurrent-controlledoscillatorcircuit.Usingathree-stageringoscillatorwithcontrolledPMOScurrentsourcesasloads,theCCOachievesbothawidetuningrangeandamaximumspeedrelativelyindependentofPMOSdevice IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.30,NO.2,FEBRUARY1995 Fig.15.Mixer-LPF-currentamplier.characteristics.SincethevoltageswingsintheCCOarenotrail-to-rail,thePMOSloadsareinsaturationforthemostpartandhencetheirgate-channelcapacitancehasnegligibleeffectonthespeed.Also,withasmallspeedpenalty,thetransconductanceofthePMOSransistorscanbeminimizedtoreducetheircontributiontotheCCOphasenoise.Notethatallthedevicesarering-shapedhere.Astheoscillatoremploysacurrent-modecontrolsignal,itachievesarelativelylowsensitivitytocommon-modeeffects.Simulationsindicatethatthesensitivityoftheoscillationperiodtothesupplynoiseis30timeslessthanthatofthecasewherethePMOSloadsarecontrolledbyavoltage.Fig.15depictsthemixer-LPF-ampliercascade.Transistors ± constituteanexclusiveNOR(XNOR)gate, and formtheLPF,and ± operateasacurrentamplier.Thebiasvoltage isapproximatelyequalto and functionsascoarsefrequencycontrol.TounderstandtheoperationoftheXNORgate,notethatwhen islow,only and areactiveand .Similarly,when islow, .Thus, IncontrasttotheconventionalCMOSXOR[3],thepro-posedmixerhastwoadvantages:1)itisinherentlysymmetricwithrespecttoinputs and ,andhencefreefromsystematicphaseerror;2)itdoesnotrequirecomplementaryinputs,relaxingthedesignwithhigh-speedCMOSsignals.Thecircuitincorporatesthering-shapedgeometryforallthedevices,withtheirlow-capacitanceterminalsconnectedtonodes and EmployingonlyNMOStransistorsforhighspeedandhighmixinggain,thistopologydissipatessomestaticpowerwhen or ishigh,anonethelessminorissueatanoperatingspeedof3GHz.Aninterestingissuerelatedtomixingarisesindeepsub-micronCMOStechnologies.Whileforchannellengthsofapproximately1 mandabove,itispossibletodesignsmall-signalmixersbasedonthesquare-lawMOSI-Vcharacteristics[8],velocitysaturationinsubmicronCMOSmakesitdif-culttoachievesmall-signalmixing.Thisisbecausethesmall-signaltransconductanceofshort-channelMOSFET'sisrelativelyindependentoftheirbiascurrent[9]andhencecanhardlybemodulatedbysmall-signalvariationsinthatcurrent.Thus,short-channelMOSmixersrequirelargeinputsignalsatleastatoneoftheirinputs,animportantissueindesigningandinterfacingtheCCOandthemixer.(Incontrast,bipolartransistorscanperformsmall-signalmixingeveninhighlyscaledtechnologiesbecausetheircharacteristicsremainclosetoexponential.) Fig.16.SimulatedcontrolcurrentofPLLduringcapture.C.DesignConsiderationsAnimportantissueinthedesignofPLL'sisthechoiceoftheclosed-loopbandwidthandthelooplter.Inadditiontothecapturerange,twosourcesofnoisemustbeconsideredinsettingthebandwidth:theinputphasenoiseandtheoscillatorphasenoise.Toreducetheinputphasenoise,thePLLmustoperateasanarrow-bandlter,whereastosuppresstheoscillatorphasenoise,theloopmustbesufcientlyfastsoitcancorrectrandomvariationsintheoscillatorperiod.Fromtheaboveobservation,wenotethatthechoiceoftheloopbandwidthdependsontheapplicationaswellasthetechnology.Forexample,iftheoscillatorincorporates resonantdevices,its(free-running)phasenoisecanbesmallandthePLLmaybedesignedasanarrow-bandltertominimizetheinputphasenoise.Ontheotherhand,fully-monolithicoscillatorswithouthigh- componentsexhibitsub-stantialphasenoise,demandingalargeloopbandwidth.Inthisdesign,a(simulated)closed-loopbandwidthofapproximately200MHzhasbeenchosentolowertheCCOnoise.ThelooplterdeterminesboththebandwidthandthesettlingbehaviorofthePLL.InthecircuitofFig.15,theloopltertransferfunction,denedasthesmall-signaldraincurrentof dividedbytheoutputcurrentofthemixer,isgivenby (1)where and (20MHz).ThesimulatedcapturebehaviorofthePLLisdepictedinFig.16.Sincethenondominantpolesofthelooparequitelarge,theyhavelittleeffectontheclosed-loopsettlingbehavior.Whilehigherorderpolescanbecancelledbyaddingzero(s)tothelooplter,thisPLLincludesnozerosbecause,atthetimeitwasdesigned,neitherresistorsnoraccuratedevicemodelswereavailable.D.ExperimentalResultsThePLLhasbeenfabricatedinour - mCMOSprocess.ShowninFig.17isadiephotograph.Theactivearea(exclud-ingtheloopcapacitor)isapproximately60 m 100 m.For RAZAVIetal.:DESIGNOFHIGH-SPEED,LOW-POWERFREQUENCYDIVIDERS Fig.17.PLLdiephotograph.inputtermination,thesamearrangementasthedividerhasbeenused.Thecircuithasbeentestedonwaferusinghigh-speedPicoprobestoapplytheinputandsensetheoutputandaCascademulti-contactprobetoprovidepowerandgroundconnections.Alltestsareperformedatroomtemperaturewithasupplyvoltageof2.8V.Fig.18(a)and(b)showsthe3GHzoutputwaveformanditsjitterhistogram,respectively.Thejitteris2.5psrmsand20pspeak-to-peak.ThePLL(includingtheI/Obuffers)dissipates25mWatthisfrequency.Fora1.5-V inputsignal,thetrackingrangeis andthecapturerangeis MHz.ThePLLspeedandtheupperendofthetrackingrangearelimitedbytheCCOmaximumfrequency.Asthecontrolcurrentincreases,thePMOSloadsenterthetrioderegionforagreaterpartoftheswing,theequivalentgainofeachstagedrops,andthecircuiteventuallyfailstooscillate.Fig.19plotsthemaximumachievableoperatingfrequencyofthePLLversusthesupplyvoltageandFig.20showsthecorrespondingpowerdissipation.Themeasuredcapturerangeat3GHzasafunctionoftheinputsignalpowerisdepictedinFig.21.ThePLLoutputhasalsobeenexaminedinthefrequencydomain.Fig.22illustratestheCCOfree-runningoutput,indi-catingarelativelywidespectrumandhighphasenoise.Theoutputisdramaticallyimprovedinthelockmode,asshowninFig.23,exhibitingasharpspectrallineat3GHz.ThephasenoisecanbemeasuredfromFig.24tobeapproximately 100dBc/Hzat40kHzoffset. (a) Fig.18.PLLoutputat3GHz,(a)time-domainwaveform,(b)jitterhis- Fig.19.MaximumachievableoperatingfrequencyofPLLversussupplyV.CDeepsubmicronCMOSdevicesexhibitpromisingcapabil-itiesforhigh-performancecommunicationcircuits.ThelowsupplyvoltageandlowpowerofCMOStechnologieshave IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.30,NO.2,FEBRUARY1995 Fig.20.PLLpower-speedtrade-off. Fig.21.PLLcapturerangeversusinputsignalpowerat3GHz. Fig.22.PLLoutputspectrumwithfree-runningCCO(horizontalscaleMHz/div.,verticalscale=10dB/div.,resolutionbandwidthmadethemcontenderstosiliconbipolarandIII-Vdevicesevenatmulti-gigahertzspeeds.Wehavedemonstratedthispotentialina13.4GHz28mWfrequencydivideranda3GHz25mWphase-lockedloop.Usingamaster-slaveconguration,thedividercanoperatewithsupplyvoltagesaslowas1.2V,atwhichitsmaximumspeedis5GHz.ThePLLincorporatesacurrent-controlledoscillatorandafullysymmetricmixertoachieveatrackingrangeof MHzandanrmsjitterof2.5ps. Fig.23.PLLoutputspectruminthelockmode(horizontalscaleMHz/div.,verticalscale=10dB/div.,resolutionbandwidth=10 Fig.24.PLLoutputspectruminthelockmode(horizontalscale=50kHz/div.,verticalscale=10dB/div.,resolutionbandwidthTheauthorswishtothankR.Swartzforstimulatingdis-cussionsandD.Jeon,G.Chin,Y.Kim,E.Westerwick,andM.Morrisforfabricationsupport.[1]B.Razavi,K.F.Lee,andR.H.Yan,ªA13.4-GHzCMOSfrequencyISSCCTech.Dig.,pp.176±177,Feb.1994.[2]B.Razavietal.,ªA3-GHz25-mWCMOSphase-lockedloop,ºCircuitsSymp.Dig.,pp.131±132,June1994.[3]K.F.Leeetal.,ªRoomtemperature0.1-mCMOStechnologywith11.8psecgatedelay,ºIEDMTech.Dig.,pp.131±134,Dec.1993.[4]B.Razavi,R.H.Yan,andK.F.Lee,ªImpactofdistributedgateresistanceontheperformanceofMOSdevices,ºtobepublishedinIEEETrans.CircuitsSyst.ÐPartI,vol.41,pp.750±754,Nov.1994.[5]M.Fujishimaetal.,ªLow-power1/2frequencydividersusing0.1-CMOScircuitsbuiltwithultrathinSIMOXsubstrates,ºIEEEJ.Solid-StateCircuits,vol.28,pp.510±512,April1993.[6]J.YuanandC.Svensson,ªHigh-speedCMOScircuittechnique,ºJ.Solid-StateCircuits,vol.24,pp.62±70,Feb.1989.[7]K.M.Ware,H.S.Lee,andC.G.Sodini,ªA200-MHzCMOSphase-lockedloopwithdualphasedetectors,ºIEEEJ.Solid-StateCircuits,vol.24,pp.1560±1568,Dec.1989. RAZAVIetal.:DESIGNOFHIGH-SPEED,LOW-POWERFREQUENCYDIVIDERS[8]Z.Wang,ªACMOSfour-quadrantanalogmultiplierwithsingle-endedvoltageoutputandimprovedtemperatureperformance,ºIEEEJ.Solid-StateCircuits,vol.26,pp.1293±1301,Sept.1991.[9]S.M.Sze,PhysicsofSemiconductorDevices,2nded.NewYork:Wiley,1981. BehzadRazavi(S'87±M'91)receivedtheB.Sc.degreeinelectricalengineeringfromTehran(Sharif)UniversityofTechnology,Tehran,Iran,in1985,andtheM.Sc.andPh.D.degreesinelectricalengineer-ingfromStanfordUniversity,Stanford,CA,in1988and1991,respectively.HeworkedatTektronix,Inc.,Beaverton,OR,duringthesummerof1988onthedesignofhigh-speeddataacquisitionsystems,andwasaResearchAssistantattheCenterforIntegratedSystems,Stan-fordUniversity,from1988to1991.SinceDecember1991hehasbeenaMemberofTechnicalStaffatAT&TBellLaboratories,Holmdel,NJ,wherehisresearchinvolvesintegratedcircuitdesignforcommu-nicationsystems.Hiscurrentinterestsincludedataconversion,clockrecovery,frequencysynthesis,andlow-voltagelow-powercircuits.Dr.RazavihasbeenaVisitingLectureratPrincetonUniversity,Princeton,NJ,andStanfordUniversity.HeisalsoamemberoftheTechnicalProgramCommitteeoftheInternationalSolid-StateCircuitsConference.HehasservedasGuestEditortotheIEEEJOURNALOFTATEInternationalJournalofHighSpeedElectronicsandiscurrentlyanAssociateEditorofJSSC.HereceivedtheBeatriceWinnerAwardforEditorialExcellenceatthe1994ISSCC.HeistheauthorofthebookPrinciplesofDataConversionSystemDesign(IEEEPress,1995)andeditorofPhase-LockedLoopsandClockRecoveryCircuitstobepublishedbyIEEEPressin1995. KwingF.Lee(S'79±M'82)receivedtheB.S.de-greeinphysicsfromtheMassachusettsInstituteofTechnology,Cambridge,MA,in1976,andthePh.D.degreeinappliedphysicsfromStanfordUni-versity,Stanford,CA,in1982.In1982hejoinedtheHighSpeedElectronicsResearchDepartmentatBellLaboratories,Holmdel,NJ.HeiscurrentlywiththeULSITechnologyResearchDepartmentatBellLaboratories,MurrayHill,NJ.Hisresearchinterestisinhigh-speedsilicondevicesandtechnology. Ran-HongYanreceivedtheB.S.degreeinelec-tricalengineeringfromNationalTaiwanUniversityandthePh.D.degreeinelectricalandcomputerengineeringfromtheUniversityofCalifornia,SantaBarbarawherehewasinvolvedinoptoelectronicdevicesandmaterialstudiesforopticalcommuni-cationsandinformationprocessing.HejoinedtheMicrophysicsResearchDepartmentofAT&TBellLaboratoriesin1990wherehehasbeenworkingonvariousaspectsofSielectronicsresearchincludingMOStransistorscaling,highperformancedevices,novelprocessingtechniquesfordeepsubmicronCMOStechnology,andtechnology,circuit,andsoftware/systemimplicationsoflow-powerelectronics.Hehasauthoredorco-authoredmorethan80researchpapersincludingonebookchapter,andhasveissuedorpendingpatents.Dr.YanhasbeenaGuestEditorofProceedingsoftheIEEE,andservedonthetechnicalprogramcommitteeofBipolar/BiCMOSCircuitsandTechnologyMeetingandUltrafastElectronicsandOptoelectronicsConference.Hewastheorganizerfor1993IEEESolid-StateCircuitsandTechnologyCommitteeWorkshoponLowPowerElectronicsandthetechnicalprogramchairmanforthe1994SymposiumonLowPowerElectronics.HeisamemberoftheAmericanPhysicalSociety. IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.30,NO.2,FEBRUARY1995DesignofHigh-Speed,Low-PowerFrequencyDividersandPhase-LockedLoopsinDeepSubmicronCMOSBehzadRazavi,Member,IEEE,KwingF.Lee,Member,IEEE,andRanH.YanAbstractÐDeepsubmicronCMOStechnologiesofferthehighspeedandlowpowerdissipationrequiredinmultigigahertzcommunicationsystemssuchasopticaldatalinksandwirelessproducts.Thispaperintroducesthedesignoftwocommunicationcircuits,namelya1/2frequencydividerandaphase-lockedloop,fabricatedinapartiallyscaled0.1 Fig.1.CrosssectionofanNMOSdeviceinpartiallyscaledCMOSprocess.experimentalresultsofthefrequencydivideraredescribed,andinSectionIVthePLLcircuitdetailsandmeasuredperformancearepresented.II.TVERVIEWANDScalingMOSFET'stodeepsubmicrondimensionsentails mandthegateoxidethicknessto40A.Theremainingdimensionsroughlycorrespondtoatypical1 mprocess,yieldingaminimumsource/drainareaof2.2 m 2.2 m[Fig.2(a)].Sincethecontributionofsource/drainjunctioncapacitanceissubstantial,theregularstructureofFig.2(a)doesnottakefulladvantageofthedrivecapabilityprovidedbypartialscaling.Toresolvethisissue,ring-shapedtransistorssuchasthatinFig.2(b)canbeused.Inthisgeometry,theratiooftheequivalentwidthandthedrainjunctioncapacitanceisapproximatelyfourtimesthatofFig.2(a).Also,theeffectofdistributedgateresistanceisreduced,animportantissueinwide,short-channelMOSFET's[4].1995IEEE