1 CS Highlevel Features Flexible clock sources amp distribution 5 clocks from 7 sources 2 external 5 internal Selections suitable for highspeed amp lowpower operations Wide range of operating frequency ID: 733780
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Slide1
MSP432™ MCUs TrainingPart 4: Clock System & Memory
1Slide2
CS | High-level Features
Flexible clock sources & distribution:
5 clocks from 7 sources (2 external, 5 internal)
Selections suitable for high-speed & low-power operationsWide range of operating frequency10kHz to 48 MHzFine intermediate steps with dividers & tuningConfigurable & robust system:Run-time lockable configurationFailsafe mechanism with interrupts for external sourcesSlide3
CS | HF & LF Oscillators
Frequency
Oscillators
MCLKSMCLK
HSMCLK
ACLK
BCLK
Comments
HF
1-48 MHz
DCO
✔
✔
✔
Internal
integrated digitally controlled oscillator.
1-48 MHz
HFXT
✔
✔
✔
High
frequency crystal. Frequency range is SW configurable.
24MHz
MODOSC
✔
✔
✔
Internal
osc
. option for peripherals
such as
ADC
5MHz
SYSOSC
Internal, direct
clock for ADC failsafe for HFXT
LF
32kHz
LFXT
✔
✔
✔
✔
✔
Low-frequency oscillator
32kHz
128kHz
REFO
✔
✔
✔
✔
✔
Internal
low-frequency oscillator.
Failsafe* (32kHz) for LFXT
10kHz
VLO
✔
✔
✔
✔
Internal ULP
LF
oscillator
Clock selection for WDTSlide4
CS | High-accuracy tune-able DCO
6 tune-able frequency ranges
Each range has calibrated center frequency
Example: [8-16MHz] range has a calibrated 12MHz center frequencyTune-able within each frequency rangeCenter Frequency +/- 212 steps DCOTUNE registerDCO accuracy:Internal resistor: + 2.65 % [Calibrated]External resistor : +
0.4 %
[91k
Ω
+ 0.1% ]Failsafe for internal resistor mode
4
3MHz
48MHz
24MHz
12MHz
6MHz
1.5
Calibrated Center Frequency
Frequency Range
8MHz
16MHz
4MHzSlide5
Memory | Overview
5
Memory
SizeSpeed
Features
Flash
256kB + 4kB
Sector: 4kB
16MHz
Speed boost with 128-bit buffer & pre-fetchPowerful security features
SRAM64kB
Bank: 8kB48MHzDynamic bank power-down & retention options for low power
ROM
32kB48MHz
Robust DriverLib
APIs integrated to save application space
Lower power execution
BSL8kB
16MHzUART/I2C/SPI Boot-Strap Loader provided
*Possible change: programmable BSL in next devices/revisionsSlide6
Independent banks simultaneous read/execute and program/erase operations
128-bit buffer
Power savings
& higher effective speed with ARM’s pre-fetchHardware assisted operationsBurst data comparison for fixed patterns (data fill check)Flash program modes with auto-computed parity & auto-verify:Write
immediate, 128-bit full word write, or 4*128-bit burst mode
Flexible
Code
security & protection
options:Individual Flash IP sector protection, further secured/protected with MPU
Up to 4 IP-protection memory zones
6
}
128kB
Bank 1
Bank 2
4kB
4kB
4kB
256kB
Individually
[un-]protected
from write/erase
INFO
4kB
Memory |
Flash
> 10
5
erase cyclesSlide7
Memory | RAM
Up to 64KB of banked SRAM architecture
8 dynamically configurable banks:
Enable/disable banks to optimize active mode power consumptionRetain/not retain content in LPM3 to minimize SRAM leakage power consumption
SRAM banks
Memory size
Bank 0
enable/retention (always enabled)
8KB
Bank 1 enable/retention
16KBBank 2 enable/retention24KB
. . . …
Bank 6 enable/retention56KB
Bank 7 enable/retention64KBSlide8
Memory | Memory Map
0x00000000
Flash
0x01000000
ROM
0x20000000
SRAM
0x22000000
Bit-banded SRAM
0x40000000
Peripherals (Registers)
0x42000000
Bit-banded Peripherals
0xE0000000 Instrumentation, ETM, etc.
256kB + 4kB
Interrupt Vector Table
Application Code
Peripheral Driver Library
Ultra-low-leakage SRAM
64kB = 8 x 8kB banks
Bit-banded
Bit-Band
Bit-Band
Peripheral Space
Register directly accessible
Bit-bandedSlide9
Power, Clock, & Memory | Overall System Design
Regulator: DC-DC or LDO
DC-DC yields higher efficiency than LDO at higher speed
DC-DC requires longer start-up time and transitions from Sleep ModesFlash wait states @ MCLK > 12MHz for VCORE = 0@ MCLK > 16MHz for VCORE = 1VCORE level @ MCLK > 24MHz9
SystemFrequency
VCORE
LDO/DC-DC*
Flash Wait
States
0-12MHz
0
LDO0
12-16MHz0
LDO116-24MHz
0LDO
124-32MHz1
DC-DC1
32-48MHz1DC-DC
2