PPT-The Memory Hierarchy Cache, Main Memory, and Virtual Memory

Lecture for CPSC 5155 Edward Bosworth PhD Computer Science Department Columbus State University The Simple View of Memory The simplest view of memory is that presented at the ISA Instruction Set Architecture level At this level memory is a . P & H Chapter 5.4-5. Performance. Virtual Memory Summary. PageTable. for each process:. 4MB contiguous in physical memory, or multi-level, …. every load/store translated to physical addresses. Mark Gebhart. 1,2 . Stephen W. Keckler. 1,2. Brucek Khailany. 2. Ronny Krashinsky. 2. . William J. Dally. 2,3. 1. The University of Texas at Austin . 2. NVIDIA . 3. Stanford University. Methodology. Li-Shiuan Peh. Computer Science & Artificial Intelligence Lab.. Massachusetts Institute of Technology. May 2, 2012. L22-. 1. http://csg.csail.mit.edu/6.S078. Virtual Memory Basics. physical. address. Memory and Performance. Many . of the following slides are taken with permission from . Complete . Powerpoint. Lecture Notes for. Computer Systems: A Programmer's Perspective (CS:APP). Randal E. Bryant. and Cache. A Mystery…. Memory. Main memory . = . RAM. : Random Access Memory. Read/write. Multiple . flavors . DDR SDRAM most common. 64 . bit wide. DDR : Dual Data Rate. S . : Synchronous. D : synamic. Managed jointly by CPU hardware and the operating system (OS). Programs share main memory. Each gets a private virtual address space holding its frequently used code and data. Protected from other programs. Prof. . Mikko. H. . Lipasti. University of Wisconsin-Madison. Lecture notes based on notes by . Jim Smith and Mark Hill. Updated by Mikko Lipasti. Readings. Read on your own:. Review: Shen & Lipasti Chapter 3. Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — . 2. Memory Technology. Static RAM (SRAM). 0.5ns – 2.5ns, $2000 – $5000 per GB. Dynamic RAM (DRAM). 50ns – 70ns, $20 – $75 per GB. Direct-mapped caches. Set-associative caches. Impact of caches on performance. CS 105. Tour of the Black Holes of Computing. Cache Memories. C. ache memories . are small, fast SRAM-based memories managed automatically in hardware. Virtual Memory Use main memory as a “cache” for secondary (disk) storage Managed jointly by CPU hardware and the operating system (OS) Programs share main memory Each gets a private virtual address space holding its frequently used code and data Memory Hierarchy Lecture notes from MKP, H. H. Lee and S. Yalamanchili Reading Sections 5.1, 5.2, 5.3, 5.4, 5.8 (some elements), 5.9 SRAM: Value is stored on a pair of inverting gates Very fast but takes up more space than DRAM (4 to 6 transistors) Virtual Memory 2 Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University P & H Chapter 5.4 Goals for Today Virtual Memory Address Translation Pages, page tables, and memory mgmt CS 3410, Spring 2012. Computer Science. Cornell University. P & H Chapter 5.4 . Goals for Today. Virtual Memory. Address Translation. Pages, page tables, and memory . mgmt. unit. Paging. Role of Operating System. Snehasish. Kumar, . Hongzhou. Zhao†, . Arrvindh. . Shriraman. Eric Matthews∗, Sandhya . Dwarkadas. †, Lesley Shannon∗. School of Computing Sciences, Simon Fraser University. †Department of Computer Science, University of Rochester.