LiShiuan Peh Computer Science amp Artificial Intelligence Lab Massachusetts Institute of Technology May 2 2012 L22 1 httpcsgcsailmitedu6S078 Virtual Memory Basics physical address ID: 435368
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Slide1
Virtual Memory Part 1Li-Shiuan PehComputer Science & Artificial Intelligence Lab.Massachusetts Institute of Technology
May 2, 2012
L22-1
http://csg.csail.mit.edu/6.S078Slide2
Virtual Memory Basics
physicaladdress
virtual
address
machine
language
address
Address
Mapping
ISA
Physical
Memory
(Caches, DRAM)
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lw
$t0, 32($s3) 0xABCDEFGH 01HGFEDCB 32-bit ISA 1GB DRAM (230)
lw
$t0, 32($s3) 0xABCDEFGHIJKLMNOP 0xHGFEDCBA 32-bit ISA 4GB DRAM (232)
lw
$t0,
32
($s3
)
0xABCDEFGHIJKLMNOP 0xIHGFEDCBA
64-bit ISA 64GB DRAM (2
36
)Slide3
Virtual Memory Basics: Pages
physical
address
virtual
address
machine
language
address
Address
Mapping
ISA
Physical
Memory
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lw
$t0, 32($s3) 0xABCDEFGH 0xHGFEDFGH
physicaladdressvirtualaddressmachinelanguageaddressAddressMapping(Page Tables)
ISAPhysical
Memory
Mapping individual addresses incurs too much overhead:
Let’s page it: Chunk address space!
lw
$t0,
32
($
s3) Page Index:0xABCDE 0xHGFED
Page Offset:0xFGH
0xFGHSlide4
Processor generated address can be interpreted as a pair <page number, offset>A page table contains the physical address of the base of each pagePaged Memory Systems
Page tables make it possible to
access and store pages
of a program
non-contiguously
0
1
2
3
Address Space
of User-1
Page Table
of User-1
0
1
2
3
1
0
2
3
page number
offset
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Why Virtual Memory?Illusion of a large, private, uniform store
Protection & Privacy
several users, each with their private address space and one or more shared address spaces
page table
name space
Demand Paging
Provides the ability to run programs larger than the primary memory
Hides differences in machine configurations
The price is address translation on each memory reference
OS
user
i
Primary
Memory
Swapping Store
VA
PA
mapping
PageTbl
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Why Virtual Memory:Reason #1: Protection & PrivacySo: Private Address Space per User
Each user has a page table
Page table contains an entry for each user page
VA1
User 1
Page Table
VA1
User 2
Page Table
VA1
User 3
Page Table
Physical
Memory
free
OS
pages
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Address Translation & Protection
Physical Address
Virtual Address
Address
Translation
Virtual Page No. (VPN)
offset
Physical Page No. (PPN)
offset
Protection
Check
Exception?
Kernel/User Mode
Read/Write
Every instruction access and data access needs address translation and protection checks
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Why Virtual Memory:Reason #2: Demand Paging (VM >> PM)So: Page Table keeps track of disk vs. DRAM
CPU
0:
1:
N-1:
Physical
Memory (DRAM)
Load 0xf0
0:
1:
P-1:
Page Table
Store 0x10
Disk
Virtual
Addresses
Physical
Addresses
Page Faults
: Page not in DRAM,
so, load from Disk to DRAM!Slide9
Linear Page Table: Implementing Demand Paging and Protection
VPN
Offset
Virtual address
PT Base Register
VPN
Data word
Data Pages
Offset
PPN
PPN
DPN
PPN
PPN
PPN
Page Table
DPN
PPN
DPN
DPN
DPN
PPN
Page Table Entry (PTE) contains:
A bit to indicate if a page exists
PPN (physical page number) for a memory-resident page
DPN (disk page number) for a page on the disk
Status bits for protection and usage
OS sets the Page Table Base Register whenever active user process changes
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Page Tables in Physical Memory:1 memory access for translation +1 memory access for actual access! +?
VA1
User 1
PT User 1
PT User 2
VA1
User 2
Idea: cache the address translation of frequently used pages
– Translation Look-aside Buffer (TLB)
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translation
accessSlide11
A cache for address translations:Translation Lookaside Buffers (TLB)
Cache
address translations
in TLB
TLB hit
Single Cycle Translation
TLB miss
Page Table Walk to find Page Table Entry in DRAM, and refill into TLB
VPN
offset
V R W D tag PPN
physical address
PPN offset
virtual address
hit?
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Virtual Memory: Translation + Access
physical
address
virtual
address
machine
language
address
Address
Mapping
ISA
Physical
Memory
(Caches, DRAM)
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Physical Memory
handles theaccess from DRAM
Virtual Memory
handles thetranslationandfilling DRAMfrom DiskSlide13
Virtual Memory:
putting it all together
Virtual Address
TLB
Lookup
Page Table
Walk (DRAM)
Update TLB
Page Fault
(OS loads page)
Protection
Check
Physical
Address
(to
cache
hierarchy)
miss
hit
the page is Ï memory Î memory
deniedpermittedProtectionFault
hardware
hardware or software
software
SEGFAULT
Where?
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Translation
miss!
Access
miss!Slide14
Handling a TLB MissSoftware (MIPS, Alpha)TLB miss causes an exception and the operating system walks the page tables and reloads TLB.
A
privileged “untranslated
” addressing mode used for walk
Hardware (SPARC v8, x86, PowerPC)
A memory management unit (MMU) walks the page tables and reloads the TLB
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Page Fault HandlerWhen the referenced page is not in DRAM:The missing page is located (or created)It is brought in from disk, and page table is updated Another job may be run on the CPU while the first job waits for the requested page to be read from diskIf no free pages are left, a page is swapped out approximate LRU replacement policy
Since it takes a long time (msecs
) to transfer a page, page faults are handled completely in software (OS)Untranslated addressing mode is essential to allow kernel to access page tables
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Virtual memory + processor + cachesMay 2, 2012L22-16http://csg.csail.mit.edu/6.S078
PC
Inst TLB
Inst. Cache
D
Decode
E
M
Data TLB
Data Cache
W
+
TLB miss? Page Fault?
Protection violation?
TLB miss? Page Fault?
Protection violation?Slide17
Physical or Virtual Address Caches?one-step process in case of a hit (+)cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-)aliasing problems due to the sharing of pages (-)
CPU
Physical
Cache
TLB
Primary
Memory
VA
PA
Alternative: place the cache before the TLB
CPU
VA
(StrongARM)
Virtual
Cache
PA
TLB
Primary
Memory
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Aliasing in Virtual-Address Caches
VA
1
VA
2
Page Table
Data Pages
PA
VA
1
VA
2
1st Copy of Data at PA
2nd Copy of Data at PA
Tag
Data
Two virtual pages share one physical page
Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other!
General Solution:
Disallow aliases to coexist in cache
Software (i.e., OS) solution for direct-mapped cache
VAs of shared pages must agree in cache index
bits
Hardware solution
for direct-mapped cache
Cache size < Page size
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Let’s build!May 2, 2012L22-19http://csg.csail.mit.edu/6.S078
F
Fetch
fr
D
Decode
dr
R
Reg
Read
rr
X
Execute
xr
M
Memory
mr
W
Write-
back
pc
Virtual
I$
VA
TLB
I$ miss (VA)
Virtual
D$
VA
D
$ miss (VA)
Physical
L2$
PA
Page Table Walker
TLB miss
DRAM (Page Table)
Page Fault Exception
DRAM (Pages)
Page Fault