PPT-Chapter 5 Large and Fast: Exploiting Memory Hierarchy

Chapter 5 Large and Fast Exploiting Memory Hierarchy 2 Memory Technology Static RAM SRAM 05ns 25ns 2000 5000 per GB Dynamic RAM DRAM 50ns 70ns 20 75 per GB. Avg Access Time 2 Tokens Number of Controllers Average Access Time clock cyles brPage 16br Number of Tokens vs Avg Access Time 9 Controllers Number of Tokens Average Access Time clock cycles brPage 17br brPage 18br In our simple model the memory system is a linear array of bytes and the CP U can access each memory location in a constant amount of time While this is an effective model as f ar as it goes it does not re64258ect the way that modern systems really Vasileios . Karakostas. , . Jayneel Gandhi. , . Furkan. . Ayar. , . Adrián. Cristal. , . Mark D. Hill. , . Kathryn S. . Mckinley. , . Mario . Nemirovsky. , . Michael M. Swift. , . Osman S. . Ünsal. Rajeev . Balasubramonian. School of . Computing. University of Utah. Oct 2012. 2. Power Contributions. PERCENTAGE. OF TOTAL. SERVER. POWER. PROCESSOR. MEMORY. 3. Power Contributions. PERCENTAGE. OF TOTAL. and Cache. A Mystery…. Memory. Main memory . = . RAM. : Random Access Memory. Read/write. Multiple . flavors . DDR SDRAM most common. 64 . bit wide. DDR : Dual Data Rate. S . : Synchronous. D : synamic. Vasileios . Karakostas. , . Jayneel Gandhi. , . Furkan. . Ayar. , . Adrián. Cristal. , . Mark D. Hill. , . Kathryn S. . Mckinley. , . Mario . Nemirovsky. , . Michael M. Swift. , . Osman S. . Ünsal. CprE 381 Computer Organization and Assembly Level Programming, Fall 2013. Zhao Zhang. Iowa State University. Revised from original slides provided . by MKP. Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — . Hierarchy with Hi-Spade. . Phillip B. Gibbons. Intel Labs Pittsburgh. September 22, 2011. Abstract. The . goal of the Hi-Spade project is to enable a hierarchy-savvy approach to algorithm design and systems for emerging parallel hierarchies. Good performance often requires effective use of the cache/memory/storage hierarchy of the target computing platform. Two recent trends---pervasive multi-cores and pervasive flash-based SSDs---provide both new challenges and new opportunities for maximizing performance. The project seeks to create abstractions, tools and techniques that (. Storage technologies and trends. Locality of reference. Caching in the memory hierarchy. CS 105. Tour of the Black Holes of Computing. Random-Access Memory (RAM). Key features. RAM. is traditionally packaged as a chip.. 11. th. Lecture, October 2, 2018. Today. Storage technologies and trends. Locality of reference. Caching in the memory hierarchy. Random-Access Memory (RAM). Key features. RAM . is traditionally packaged as a chip.. Lecture for CPSC 5155. Edward Bosworth, Ph.D.. Computer Science Department. Columbus State University. The Simple View of Memory. The simplest view of memory is . that presented . at the ISA (Instruction Set Architecture) level. At this level, memory is a . Agenda. Logistics. Review from last lecture. O. ut-of-order execution. Data flow model. Superscalar processor. Caches. Final Exam. C. ombined.  final exam . 7-10PM.  . on Tuesday, 9 May . 2017. Any conflict?. Recovered memories. : Memories, . typically of traumatic experiences . that have been forgotten to be retrieved later.. Loftus. : No such thing as recovered memories.. Current thinking. : Some recovered memories are real, but many may be false.. Access the reports. Go to the same place where you log into ESS (. https://portal.passhe.edu/irj/portal. ). Sign into your account. Then click on the ‘Business Intelligence’ tab. . From here you will see a breakdown of report areas depending on the portal roles assigned to you. At the minimum, you will see ‘Campus Reports’ and ‘Manage Saved Views’ which are available to all users. Each area then contains individual reports. When you click on a report link, it will open in a new window. .