PPT-Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

Snehasish Kumar Hongzhou Zhao Arrvindh Shriraman Eric Matthews Sandhya Dwarkadas Lesley Shannon School of Computing Sciences Simon Fraser University Department of Computer Science University of Rochester. 15-213 / 18-213: Introduction to Computer Systems. 10. th. Lecture, Sep. . 27, 2012. Instructors:. . Dave O’Hallaron, Greg Ganger, and Greg . Kesden. Today. DRAM as building block for main memory. Lab 2: Cache Lab. Overview. Objectives. Cache Set-Up. Command line parsing. Least Recently Used (LRU). Matrix Transposition. Cache-Friendly Code. Objective. There are two parts to this lab:. Part A: Cache Simulator. Mark Gebhart. 1,2 . Stephen W. Keckler. 1,2. Brucek Khailany. 2. Ronny Krashinsky. 2. . William J. Dally. 2,3. 1. The University of Texas at Austin . 2. NVIDIA . 3. Stanford University. Methodology. and Cache. A Mystery…. Memory. Main memory . = . RAM. : Random Access Memory. Read/write. Multiple . flavors . DDR SDRAM most common. 64 . bit wide. DDR : Dual Data Rate. S . : Synchronous. D : synamic. Hierarchy with Hi-Spade. . Phillip B. Gibbons. Intel Labs Pittsburgh. September 22, 2011. Abstract. The . goal of the Hi-Spade project is to enable a hierarchy-savvy approach to algorithm design and systems for emerging parallel hierarchies. Good performance often requires effective use of the cache/memory/storage hierarchy of the target computing platform. Two recent trends---pervasive multi-cores and pervasive flash-based SSDs---provide both new challenges and new opportunities for maximizing performance. The project seeks to create abstractions, tools and techniques that (. 10 Nov, 2015. Instructor:. . Rabi Mahapatra. Slide Source: Randal E. Bryant and David R. . O’Hallaron. Today. Storage technologies and trends. Locality of reference. Caching in the memory hierarchy. Storage technologies and trends. Locality of reference. Caching in the memory hierarchy. CS 105. Tour of the Black Holes of Computing. Random-Access Memory (RAM). Key features. RAM. is traditionally packaged as a chip.. 11. th. Lecture, October 2, 2018. Today. Storage technologies and trends. Locality of reference. Caching in the memory hierarchy. Random-Access Memory (RAM). Key features. RAM . is traditionally packaged as a chip.. Lecture for CPSC 5155. Edward Bosworth, Ph.D.. Computer Science Department. Columbus State University. The Simple View of Memory. The simplest view of memory is . that presented . at the ISA (Instruction Set Architecture) level. At this level, memory is a . Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — . 2. Memory Technology. Static RAM (SRAM). 0.5ns – 2.5ns, $2000 – $5000 per GB. Dynamic RAM (DRAM). 50ns – 70ns, $20 – $75 per GB. Memory Hierarchy Lecture notes from MKP, H. H. Lee and S. Yalamanchili Reading Sections 5.1, 5.2, 5.3, 5.4, 5.8 (some elements), 5.9 SRAM: Value is stored on a pair of inverting gates Very fast but takes up more space than DRAM (4 to 6 transistors) Aditya Shah. Recitation 7: Oct . 8. th. , 2015. Welcome to the World of Pointers !. Outline. Schedule. Memory . organization. Caching. Different . types of locality. Cache organization. Cache lab. Part (a) Building Cache Simulator. Eliminating Waste . in the Memory Hierarchy. Snehasish Kumar. Arrvindh. . Shriraman. Eric Matthews. Lesley Shannon. Hongzhou. Zhao. Sandhya. . Dwarkadas. Fixed granularity cache . organisation. Tag Array. Hagersten. , . Landin. , and . Haridi. (1991). Presented by Patrick . Eibl. Outline. Basics of Cache-Only Memory Architectures. The Data Diffusion Machine (DDM). DDM Coherence Protocol. Examples of Replacement, Reading, Writing.