Work Package 5 IC Technologies - PowerPoint Presentation

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Work Package 5IC Technologies

Michael Campbell and Federico

Faccio

Microelectronics Section

ESE Group, EP Department, CERN

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10um

3um

1.5um

1um

0.8um

0.35um

0.25um

180nm

65nm

130nm

Moore’s uncertain future

Alice SPD chip 1999

RD-53 chip

2017

2

Slide3

Si CMOS technology nodes in papers ISSCC 2018

65 nm

14 nm

~300 papers acceptance <40%

'

SiGe

'

Slide by E. Heijne

From ISSCC 2018

28 nm

3

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Looking ahead – scaling

As a community we have accumulated (at least) 10 years delay since 1999

With the 65nm process we cannot increase IO speed beyond 10Gbps

FPGA chips (which we rely on off-detector) are pulling away from us

We cannot stand still but going forward requires significant resources

Below 28nm

FinFETs

become the workhorse

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Slide5

Organisation of Work Package

5

K Kloukinas

M. Campbell

R Ballabriga

S.

Michelis

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Organisation of Work Package

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Organisation of Work Package

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1a CMOS Technologies - summary

Survey CMOS technologies available

28nm planar

16nm

FinFET

Understand fundamental radiation hardnessAt this point is would be helpful to know the kind of machine being planned (CLIC, HE-LHC, FCC-pp, FCC-

ee) as the requirements can vary by 5-6 orders of magnitude!Prepare infrastructure for accessNDA permitting collaborative design and access to MPW and engineering runs

Design kits and EDA toolsTraining for designers

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1a CMOS Technologies – some technical detailsPlanar vs FinFET

9

Planar

p-substrate

channel

p-well

gate

n

+

drain

n

+

source

STI

p-well tie

FinFET

fully-depleted

body

p-substrate

n

+

drain

p-well

STI

NMOS

n

+

source

p-well tie

Slide courtesy of Alvin

Loke

, Qualcomm

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1a CMOS Technologies – some technical details

Power efficiency gain

FinFET

M. G. Bardon (IMEC)

ICICDT

(2015)

Gate length shrink

Performance scaling

FET is on edge

Dual gate

Reduces

I

off

Courtesy of Michael P. King, Sandia

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1a CMOS Technologies – some practical details

NDA’s take an age to negotiate but are an absolute necessity to enable

collaborative

work. They must also be scrupulously respected.

Confidential foundry information

Use restrictions

Export controls

Access to high end design tools is going to be essential for successful submissions in the new processes

Europractice needs our strongest support!

Training of existing and new designers in the use of the new tools and with an awareness of radiation tolerant design practices will be essential

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Organisation of Work Package

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1b Assembly technologies – summary

Hybrid pixel detectors will continue to be needed in the regions of the experiments with high hit rates

TSV processing allows increased data throughput as data can be extracted from anywhere in the pixel matrix

In the long term access to commercial processes where wafer stacking permits the connection of a sensor and an electronics layer will blur the lines between hybrid and monolithic detectors

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1b Assembly technologies – some technical detailsTSV processing

TSV processing compatible with bump bonding exists already in 130nm technology (8” wafers)

It will be developed for 65nm technology (12” wafers) in the context of the Timepix4 development

In the work package it will be adapted to 28nm (or lower) technology

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Lot

no. uSA999P

Lot no. uSB254P

Wafer number

P04

P05

P06

P01

P02

P03

% KGD

before TSV (on wafer)

57

51

50

50

60

53

% KGD after TSV (chips)

45

41

rework

20

41

38

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1b Assembly technologies – some technical detailsWafer stacking

Wafer level stacking @ pixel pitch 6.9

m

m

SONY imaging chip with on-pixel ADC

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Slide by E. Heijne

ISSCC 2018

90nm CIS

65nm CMOS

M.

Sakakibara

et al. paper 5.1, ISSCC 2018

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Organisation of Work Package

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Organisation of Work Package

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Evaluate ASIC technologies for analog design, build up experience in using them

Design circuit building block and characterise them on silicon

Encourage the participation of other Institutes from the HEP ASIC community

Disseminate the produced know-how and contribute to the diffusion of a first-time working silicon culture

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2a Low voltage and low power design - summary

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Build-up experience in the use of the mainstream CMOS technology chosen in activity 1

Disseminate the know-how in the HEP community

2a Low voltage and low power design– some technical details

Design

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2a Low voltage and low power design– some technical details

Tentative list of the blocks to be developed, documented and made available:

Front-end:

Amplification, filtering and discrimination (A/D conversion) for 2-D readout circuits (Charge sensitive amplifier, shaper and comparator for sensors with input capacitance <100fF and leakage current per pixel <20nA)

Amplification, filtering and discrimination (A/D conversion) for a 1-D readout circuit (strip detectors)

Input stage and discrimination for the readout of detectors with intrinsic amplification for timing layers (

SiPMs

, MCPs)

Voltage references

Module controller:

Analog to Digital Converter (e.g. with the sigma delta architecture), Digital to Analog Converters, Temperature monitor

Data transmission and timingPLLs, DLLs, TDC

Line drivers/receivers (specifications to be defined with WP6 (High speed links))

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Organisation of Work Package

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Develop components/macroblocks for a modular power distribution scheme:

First-stage step-down POL converter from 25V to 2.5-1.8V

Macroblock step-down to be embedded in Systems-on-Chip

Macroblock linear regulator to be embedded in Systems-on-Chip

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2b Power distribution - summary

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2b Power distribution – some technical details

DCDC converters

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Today and in the near future:

Vin = 11-12V

Radiation:

TID < 150

Mrad

NIEL < 2e15 n/cm

2

FEAST2,

bPOL12V

More than 60,000 FEAST2 already supplied.

Si-strip trackers rely on bPOL12V for HL-LHC.

These designs use a 350nm

technology selected in 2007-2009

We need to ensure the long-term availability of this crucial function:

New technologies have become available (Silicon but also the very promising and fast spreading

GaN

)

Qualification for radiation effects is a long process

New assembly technologies might become essential, especially in the case of

GaN

As we have painfully experienced, these are very complex components with surprising radiation effects

–

and a requirement for high reliability

Improved input voltage rating if possible: 25V

At least a comparable radiation tolerance, but better if possible

Small footprint, magnetic-field tolerant

Target:

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2b Power distribution – some technical details

SoC Macroblocks

Systems-on-Chip use different voltage (or power) islands

to minimize power consumption

With a single supply voltage from the board, power management macroblocks on-chip

are needed to separately supply

the different islands

We propose to develop macroblocks to enable SOC power management:

A DCDC converter (capacitor or inductor based) to step down from an input voltage of 1.8-2.5V to the required voltage

A linear regulator with very low drop-out to locally and precisely regulate the voltage supply for very sensitive circuitry

These macroblocks will be designed in the mainstream CMOS technology chosen in activity 1, and will be documented and made available to users in the HEP community

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25

year1

year2

year3

year4

year5

Tech. survey, radiation studies, technology choice

Voltage Refs, T monitor

, detector

readout

TSV test runs in chosen process

1

st

stage: Tech. survey, radiation studies

Frame contract, design platform

Full support, training to HEP

Data transmission blocks

DAC, ADC

1st stage: Prototyping

Large scale testing

Macroblock for SOC:

Prototyping

5.1a CMOS Technologies

(K. Kloukinas)

5.1b CMOS-related Assembly Technologies

(M. Campbell)

5.2a Low-voltage and low-power design

(R. Ballabriga)

5.2b Power distribution

(S.

Michelis

)

Prototyping in wafer stacked CMOS

Full chip wafer stacked CMOS

Summary Timeline