of the lecture Chandana 1 Introduction 2 Example 3 Definition 4 Vector table and Maskable nonmaskable interrupts Hao ID: 246618
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Outline of the lecture:Chandana:1. Introduction2. Example 3. Definition 4. Vector table and Maskable/nonmaskable interrupts ________________________________________________Hao:5. Stack status 6. HPRIO 7. Example
Introduction to InterruptsSlide2
Polling and Interrupts
Polling- Imagine a phone without a bell. You would have to periodically answer the phone to see if anyone is thereInterrupt – Phone with a bell. You can do something else and stop and answer the phone when it rings2Slide3
Polling Pros and Cons
ProsSimple ImplementationGood for single I/O casesDoesn’t need extra hardwareConsInefficient for complex systemsMay not be fast enough for requirements3Slide4
Interrupts Pros vs. Cons
ProsEfficient for complex systems (great multitasking)Can be ignored (masked)Can be prioritizedConsTradeoff of hardware complexityCan make debugging difficult due to unanticipated random occurrences4Slide5
Applications
5Computer KeyboardStability Control System on CarHouse security systemPause button on televisionSlide6
Ways Interrupts can be generated
Hardware InterruptsPeripherals such as a printer or fax machineComputer Operator via keyboard, mouse or power on reset buttonAnother computerSoftware InterruptsTimer resetsTimer interruptsTrapsRequest for input or outputArithmetic overflow error6Slide7
Some Definitions
Interrupt Service Routine (interrupt handler): This is a “more important” instruction code that interrupts your main program code. The routine is specific to the type of interrupt called.Interrupt Vector: This is an address in memory where the ISR instruction code is located. It is the starting address of the code. (Like a pointer)Interrupt Vector Table: This is a table indicating the interrupt vector7ISR CodeBlah blah blah
Blah blah blah
Blah blah blah
Blah blah blah
RTI
Main Program
Blah blah blah
Blah blah blah
Blah blah blah
Blah blah blah
$FFF6Slide8
Interrupt Flow
Interrupt conditionis metRestore Registersw/ org. ValuesStandard InterruptTable
Analyze Priority
Store all registers
on the Stack
Mask(s) set?
Continue
Program
Complete Current
Instruction
A
Set (I) or (X)
to prohibit another
Interrupt
Load Address in
appropriate vector
YES
NO
ISR instruction
Clear I or X bit in
CCR
RTI
YES
NO
B
B
ASlide9
Non-Maskable Interrupts
96 Non-Maskable InterruptsHigher Priority than maskable interruptsCan interrupt Maskable Interrupt ISRsX=1 ONLY disables XIRQ interrupt (and all other interrupts are still enabled when X=1)
POR of RESET pin
Clock monitor reset
COP watchdog reset
Unimplemented instruction trap
Software interrupt (SWI)
XIRQ interruptSlide10
XIRQ & IRQ
10Slide11
Non-Maskable Interrupts
At Reset or during Non-Maskable interruptX=1 and I=1Interrupts cannot be servicedClear X bitTAP instructionANDCC #$40 instructionSoftware cannot set X bit once cleared unless non-maskable interrupt occursRTI restores X and I bits to pre-interrupt stateSlide12
Non-Maskable Interrupts
XIRQExternally triggeredPE0 pin low = XIRQ interruptSWIAllows an interrupt without an eventMON12 in use: jumps back to DBug12Unimplemented Instruction TrapCPU is given code with invalid opcodeGenerates interrupt request to unimplemented instruction trap vector12Slide13
Maskable Interrupts
27 Maskable InterruptsGlobal Masking: controls execution of all maskable interrupts (ie. I bit =1, no maskable interrupts occur)Local Masking: controls execution of interrupt on a peripheral device (ie. ATD)13IRQReal-Time Interrupt
Standard Timer Channel 0
Standard Timer Channel 1
Standard Timer Channel 2
Standard Timer Channel 3
Standard Timer Channel 4
Standard Timer Channel 5
Standard Timer Channel 6
Standard Timer Channel 7
Standard Timer Overflow
Pulse Accumulator A Overflow
Pulse Accumulator Input Edge
SPI transfer Complete
SCI system
ATD
Port J
CRG PLL Lock
CRG Self Clock Mode
Flash
CAN Wakeup
CAN Errors
CAN Receive
CAN Transmit
Port P
PWM Emergency Shutdown
VREG LVISlide14
Maskable Interrupts
14IRQOnly external maskable interrupt signalIRQE bit on IRQCR RegisterIRQE=1: High level-SensitiveIRQE=0: Low Level-SensitivePeripheral Subsystems (all other
Maskable
Interrupts)
Flag bit and interrupt enable bit
ATD, Timers, PWM, serial communications, etc
.Slide15
Interrupt Vector Tables
15Slide16
Interrupt Vector in Mon12
16MON12’s calls ISR’s specified by the user in the $0Fxx rangeThe microcontroller calls ISR’s specified in the $FFxx range.MON12 interrupt vectors are used. ($0F00-$0FFF )Slide17
Interrupts: Stack
CCR
ACC B
ACC A
X HI
X LO
Y HI
Y LO
RTN HI
RTN LO
First Pushed In
Last Pulled Off
Last Pushed In
First Pulled Off
Higher Address
Lower Address
Stack Pointer before Interrupt
Stack Pointer after Interrupt
RTN – address of next instruction in Main Program, upon return from interrupt.
X LO and Y LO are the low bytes of X and Y registers.
X HI and Y HI are the high bytes of X and Y registers.
ACC A and ACC B are the accumulators.
CCR is the Code Condition RegisterSlide18
Highest Priority Interrupt (HPRIO) Register
HPRIO register moves one maskable interrupt to top of priority list
Address: $001F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
1
1
1
1
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
-
Cannot change priority of non-
maskable
interrupts
Procedures to increase priority of
maskable
interrupt:
Set I bit to disable
maskable
interrupts
Write
low byte
of the
starting
interrupt vector address to HPRIO
Clear I bit to re-enable
maskable
interruptsSlide19
Highest Priority Interrupt Register (HPRIO)
Address: $001F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
1
1
1
1
0
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
-
PSEL[7:1] – Priority Select Bits
Write
the low byte of the
starting
maskable
interrupt vector to HPRIO to elevate that
maskable
interrupt to the highest priority
Ex: writing $
DE (#%11011110)
to HPRIO elevates the Standard Timer Overflow to highest priority (
Standard Timer Overflow
vector = $
FF
DE
&
$FFDF
)Slide20
ATD Interrupt Example : ISR
Write an Interrupt Service Routine (ISR) to be run to print out the ATD results when conversion is finishedOther programs still running during the conversionContinuous conversionCHECK LDX #ATDSTAT0 BRCLR $00,X #%1000000 CHECK * Wait until conversion completes
Polling code from our Lab 2:Slide21
ATD Interrupt Example : ISR
*Interrupt Service RoutineORG $2000LDAA ATDDR0HSTAA LSTCONVLDAA #$00 *Load D with LSTCONV LDAB LSTCONVLDX #51 *Load x with #51IDIV *Divides D by X ->D:XXGDXADDB #$30STAB V1 *Stores B to v1
XGDX
LDAA #10 *Load A with 10
MUL *Multiply A and B (low byte of D)
LDX #51
IDIV
XGDX
ADDB #$30
STAB V2 *Stores B to
v2
LDX #STRING1
JSR
OUTSTRG
LDAA #%00010000 *Scan=0,
MULT=0, CC:CA=000 (
AN0
)
STAA ATDCTL5 *Start
Conversion by setting ATDCTL5
RTI
Define a starting address
Read
ATD result
register
Store
value
to a reserved memory location
Convert value and print to
screen
Writing to ATDCTL5, only convert data from AN0
Ensures that we will get the next
interrupt (SCF is cleared)
Finally, call RTI to return from the ISR and pull
CPU register
values back from the stackSlide22
ATD Interrupt Example: Setup
Set up interrupt vector table for the ATD InterruptWrite the address of the first instruction of the ISR ($2000) to ATD interrupt vector ($0FD2)
Enable ATD interrupt
Setting
ASCIE
bit (ATDCTL2) to enable ATD interrupts (local mask)
Enable global
maskable
interrupts
Processor is then free to run other codeSlide23
ATD Interrupt Example: Setup
ORG $1000 SEI LDX #$2000 STX $0FD2 LDAA #%10000010
STAA
ATDCTL2
LDAA #%00001000
STAA ATDCTL3
LDAA #%10000101
STAA ATDCTL4
LDY
#
100
L1 DEY
BNE
L1
CLI
LDAA #%00000000
STAA ATDCTL5
Store
the address of our ISR ($2000) to the Interrupt Vector for the
ATD
($0FD2)
Set the
ASCIE bit
(bit 1 in ATDCTL2) to
enable local
ATD interrupts
Set that only one conversion each sequence
Set ATD resolution and
prescale
Wait for the
ATD
to fully power
up
Clear
the I-bit to enable all
maskable
interrupts
Starting conversion by setting ATDCTL5,
Scan=0,
MULT=0,
CC:CA=000 (
AN0
)
Set I bit to make Interrupt Vector Table changes safeSlide24
ATD
Interrupt Example: Full Code
ATDCTL2
EQU
$
0082
ATDCTL3 EQU $0083
ATDCTL4 EQU $0084
ATDCTL5 EQU $
0085
ATDSTAT0 EQU $
0086
ATDDR0H EQU $0090
LSTCONV
EQU $800
OUTSTRG EQU $FF5E
ORG $802
STRING1 FCC "The voltage is "
V1 RMB 1
FCC " . "
V2 RMB 1
FCC " Volts"
FCB $0A,$0D,$04
ORG $1000
SEI
LDX #$2000 *
Start address
of ISR
STX $0FD2 *ATD Service Routine
Vector
LDAA #%10000010 *ADPU = 1,
ASCIE=1
, ASCIF=0
STAA
ATDCTL2
LDAA #%00001000 *
one conversion each sequence
STAA ATDCTL3
LDAA #%10000101
*Resolution and
prescale
STAA ATDCTL4
LDY
#100
*ATD Converter Startup Delay
L1 DEY
BNE
L1
CLI
LDAA
#%00000000 *Scan=0, MULT=0,
CC:CA=000 (AN0) STAA ATDCTL5 *Start Conversion by setting ATDCTL5
………… *All kinds of programs
Loop *******
*Many other calculations may be performed here ******JMP Loop
SWIEND
*Interrupt Service
Routine
ORG $2000LDAA ATDDR0HSTAA LSTCONVLDAA
#$00 *Load D with LSTCONV LDAB LSTCONVLDX #51 *Load x with #51
IDIV *Divides D by X ->D:XXGDXADDB #$30
STAB V1 *Stores B to v1 XGDX
LDAA #10 *Load A with 10MUL *Multiply A and B (low byte of D)LDX #51IDIV XGDXADDB #$30
STAB V2 *Stores B to v2LDX #STRING1JSR
OUTSTRG
LDAA #%00010000 *Scan=0,
MULT=0, CC:CA=000 (
AN0
)
STAA ATDCTL5 *Start
Conversion by setting ATDCTL5
RTI
Define Constants
(ex: ATDCTL4)
Define Strings and reserve memory
Setup ADC and
ADC Interrupt
Run any other code
Convert value and print to
screen
Interrupt Service Routine
Start next conversion
Back to main program