PPT-EE 414 – Introduction to VLSI Design

Author : myesha-ticknor | Published Date : 2016-11-25

Module 6 Combinational Logic Agenda Combinational Logic nInput Gates amp Equivalent Inverter AOIOAI Logic Synthesis Transmission Gates Layout of Complex Logic

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EE 414 – Introduction to VLSI Design: Transcript

Module 6 Combinational Logic Agenda Combinational Logic nInput Gates amp Equivalent Inverter AOIOAI Logic Synthesis Transmission Gates Layout of Complex Logic Announcements. V Kamakoti Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai 600 036 India Email kamacsiitmernetin CAD for VLSI DESIGN I CAD for VLSI Design I Course Starts Here All The Best CAD for VLSI DESIGN I Evo Kamakoti and Shankar Balachandran Overview of this Lecture Types of CAD tools Why HDLs are needed Recap Gajskis Chart Abstraction Levels Recap Design Representation module det ctor XinclkRIZout input XinclkRI output Zo Kamakoti and Shankar Balachandran brPage 2br Flipflops with Asynchronous Preset and Clear Inferring a flipflop with Asynchronous Preset and Clear comes out of a combination of clocked and nonclocked events inside an always blocks sensitivity Kamakoti and Shankar Balachandran brPage 2br Overview of the lecture Blocking and Non Blocking procedural assignments Understanding the difference Blocks with mix of both assignments hybrid case Importance of the same in simulation brPa International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013 24 these three types of powers are highly dependent on supply voltage. In majority of the cases, the voltag Module #6 – Combinational Logic. Agenda. Combinational Logic. - n-Input Gates & Equivalent Inverter. - AOI/OAI Logic Synthesis. - Transmission Gates. - Layout of Complex Logic . Announcements. VLSI Design Verification and TestFaults IICMPE 6462(10/11/06)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Stuck-Open FaultsConsider a 2-input NOR gate: Stuck-Atfaults include:A-SA0, Very-large-scale integration. (. VLSI. ) is the process of creating an . integrated circuit. (IC) by combining thousands of . transistors. into a single chip. .. . VLSI began . in the . 1970s when complex . Tufts University. Instructor: Joel . Grodstein. joel.grodstein@tufts.edu. Lecture 6: Discrete voltage and frequency switching. DVFS. What we’ll cover. DVFS: why we care. What is DVFS. Effects on clocking. Tufts University. Instructor: Joel . Grodstein. joel.grodstein@tufts.edu. Lecture 7: Dark silicon. Resources. The future of microprocessors. , . Shekhar. . Borkar. 2011. “The past 20 years were the ‘great old days’; the next 20 years will hopefully be the ‘pretty good new days’ ”. EE 194: Advanced VLSI Spring 2018 Tufts University Instructor: Joel Grodstein joel.grodstein@tufts.edu Verification What is verification? The design process (highly simplified) Talk to your customer EE 194 Advanced VLSI Spring 2018 Tufts University Instructor: Joel Grodstein joel.grodstein@tufts.edu Lecture 2: Moore's Law, Scaling and power Technology scaling Everyone has heard of Moore’s Law. It’s probably been mentioned in most newspapers at some point. But what does it really mean? EE 194 Advanced VLSI Spring 2018 Tufts University Instructor: Joel Grodstein joel.grodstein@tufts.edu Lecture 8: Biological computing Computers are made of… Transistors. Lots of them! How many transistors on an Nvidia Volta? Module #4 – CMOS Fabrication. Agenda. CMOS Fabrication. - Yield. - Process Steps for MOS transistors. - Inverter Example. - Design Rules. - Passive Components. - Packaging. Announcements.

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