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PISCES: A Programmable, Protocol-Independent Software Switch PISCES: A Programmable, Protocol-Independent Software Switch

PISCES: A Programmable, Protocol-Independent Software Switch - PowerPoint Presentation

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PISCES: A Programmable, Protocol-Independent Software Switch - PPT Presentation

Muhammad Shahb az Sean Choi Ben Pfaff Changhoon Kim Nick Feamster Nick McKeown and Jennifer Rexford P4 OVS Fast Forwarding Also appears at SIGCOMM 2016 2 http ID: 736973

pipeline ovs packet action ovs pipeline action packet match editing performance tor hypervisor parser egress ingress development post copy

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Slide1

PISCES: A Programmable, Protocol-Independent Software Switch

Muhammad Shahbaz, Sean Choi, Ben Pfaff, Changhoon Kim, Nick Feamster, Nick McKeown, and Jennifer Rexford

P4

+ OVS ==

Fast Forwarding!Slide2

Also appears at SIGCOMM 2016!2

http://goo.gl/wmBmTu Slide3

Importance of Software Switches

Hypervisor

OVS

VM

VM

VM

VM

Hypervisor

OVS

VM

VM

VM

VM

OVS

VM

VM

VM

VM

Hypervisor

Hypervisor

OVS

VM

VM

VM

VM

ToR

ToR

ToR

ToR

3

CoreSlide4

Importance of

Software Switches

Hypervisor

VM

VM

VM

VM

Hypervisor

VM

VM

VM

VM

VM

VM

VM

VM

Hypervisor

Hypervisor

VM

VM

VM

VM

ToR

ToR

ToR

ToR

4

Core

OVS

OVS

OVS

OVSSlide5

Ease of

Customization?

OVS

VM

VM

VM

VM

Hypervisor

ToR

Enable

Rapid Development

and

Deployment

of

Network Features!

Is it

REALLY the case?

5

CoreSlide6

Ease of Customization?

VM

VM

VM

VM

Hypervisor

Hypervisor

VM

VM

VM

VM

For example, OVS supports following tunneling protocols:

VXLAN

: Virtual Extensible LAN

STT

: Stateless

Transport

Tunneling

NVGRE

: Network Virtualization Generic

Routing

ToR

ToR

6

Core

OVS

OVS

What about adding

new protocols?Slide7

Fast Packet IO (or Forwarding)

Rapid Development & Deployment?

7

OVS

Kernel

DPDKSlide8

Rapid Development & Deployment?

8

Packet Processing Logic

OVS

Kernel

DPDK

Parser

Match-Action Pipeline

Requires domain expertize in:

Network

protocol design

Software development

Develop

Test

Deploy

… large, complex codebases.

Maintaining changes

across

releases

A

rcane APIs

Can

take

3-6 months

to get a

new

feature

in

.Slide9

Rapid Development & Deployment?

9

Kernel

DPDK

Parser

Match-Action Pipeline

OVSSlide10

Rapid Development & Deployment?

10

Kernel

DPDK

Parser

Match-Action Pipeline

OVSSlide11

Rapid Development & Deployment?

11Kernel

DPDK

OVS

P4

Parser

Match-Action Pipeline

Compile

Parser

Match-Action Pipeline

Native OVS

341

lines of code

14,535

lines of codeSlide12

Rapid Development & Deployment?

12Kernel

DPDK

OVS

P4

Parser

Match-Action Pipeline

Parser

Match-Action Pipeline

Performance overhead!

CompileSlide13

What’s the cost of programmability on Performance

?13Slide14

PISCES: A Protocol-Independent Software Switch

14PISCESvSwitchP4

OVSSlide15

PISCES: A Protocol-Independent Software Switch

15Compiler

P4

OVS

parse

match

action

Executable

Runtime Flow Rules

Flow Rule CheckerSlide16

PISCES: A Protocol-Independent Software Switch

P4 and OVS packet forwarding models.Performance overhead of a naïve mapping from P4 to OVS.PISCES compiler optimizations to reduce the performance overhead.Slide17

P4 Forwarding Model (or Post-Pipeline Editing)

17PacketParser

Match-Action

Tables

Packet

Deparser

Ingress

Egress

Header

Fields

Ingress Packet

Egress PacketSlide18

OVS

Forwarding Model (or Inline Editing)18PacketParser

Match-Action

Tables

Ingress

Egress

Egress Packet

Ingress PacketSlide19

(Modified) OVS Forwarding Model

19PacketParser

Match-Action

Tables

Packet

Deparser

*

Ingress

Egress

Supports both editing modes:

Inline Editing

Post-pipeline EditingSlide20

Naïve Mapping from P4 to OVS

A naïve compilation of L2L3-ACL benchmark applicationPerformance overhead of~ 40%20Slide21

Causes of Performance Degradation

PacketParser

Match-Action

Pipeline

Packet

Deparser

Ingress

Egress

CPU Cycles per Packet

21Slide22

Causes of Performance Degradation22

Factors affecting CPU cycles:Extra copy of headers in the post-pipeline editing modeFully-specified checksum calculationRedundant parsing of header fields and more …Slide23

Causes of Performance Degradation

Post-pipeline editing consumes 2x more cycles than inline editing when parsing VXLAN protocol.Editing ModePros

ConsPost-Pipeline

Extra copy of headers

Inline

No extra copy of headers

Factor #1:

Extra copy of headersSlide24

Causes of Performance Degradation

Editing ModeProsConsPost-PipelinePackets are adjusted onceExtra copy of headersInline

No extra copy of headersMultiple adjustments

to packet

Factor #1:

Extra copy of headers

Inline editing

Post-pipeline editingSlide25

Causes of Performance Degradation

Factor #2: Fully-Specified ChecksumsChecksum (

version, ihl,

diffserv

,

totalLen

,

identification, flags,

fragOffset

,

ttl

, protocol,

hdrChecksum

,

srcAddr

,

dstAddr

)

Incremental-Checksum

(

ttl

)

Packet

Deparser

Egress

Packet

Parser

Ingress

decrement(

ttl

)Slide26

Causes of Performance Degradation

Factor #3: Redundant parsing of headersPacketDeparser

Egress

Packet

Parser

Ingress

Match-Action

Pipeline

L2

L2

L4

L3Slide27

Optimizing for CPU Cycles27

OptimizationsInline vs. post-pipeline editingIncremental checksumParser specializationAction specializationAction coalescingSlide28

Optimizing for CPU Cycles

OptimizationsInline vs. post-pipeline editingIncremental checksumParser specializationAction specializationAction coalescing

28Extra Copy of Headers

Fully-Specified Checksum

Redundant ParsingSlide29

Optimizing for CPU Cycles29

OptimizationsInline vs. post-pipeline editingIncremental checksumParser specializationAction specialization

Action coalescingSlide30

Optimized Mapping from P4 to OVS

Performance overhead of< 2%All optimizations together 30Slide31

Another Cause for Performance Degradation

PacketDeparser*

Egress

Packet

Parser

Ingress

Match-Action

Cache

Match-Action

Tables

Cache Misses

31

Optimizations

Cached

field modifications

Stage assignmentSlide32

Next Steps

32Support for stateful memories

and INT

Integration with the

mainline OVS

Interning at VMware to make this happen!Slide33

Summary

33With appropriate compiler optimizations

… P4

+ OVS == Fast Forwarding!Slide34

Learn

more and try PISCES here: https://github.com/P4-vSwitch Muhammad Shahbazmshahbaz@cs.princeton.edu

34

Questions?